This paper presents a Minimum Stress Factor Tracking (MSFT) algorithm designed for a T-Type Dual Active Bridge (DAB) DC-DC converter, aimed at electric vehicle (EV) charging applications. The proposed system dynamically selects among six different modulation configurations by evaluating a weighted combination of three normalized stress factors: Semiconductor Component Stress Factor (SCSF), Capacitor Component Stress Factor (CCSF), and Transformer Winding Component Stress Factor (WCSF). Each stress factor is mathematically modeled across the full operating range, allowing real-time optimization without dependency on runtime simulations. The weighting factors are user-defined and sum to unity, offering flexibility to adapt the stress minimization strategy according to specific reliability requirements. The results demonstrate that the proposed approach achieves significant stress reduction on critical components while maintaining full controllability and capacitor voltage balance. This methodology addresses a seldom-explored aspect in the current literature, opening a new path for reliability-oriented optimization in T-Type DAB converters for EV charging systems.

This paper presents an area-efficient 0.8 V current-mode bandgap reference (BGR) in 22nm fully-depleted silicon-on-insulator (FD-SOI) CMOS process. Implementing the body bias technique allows for smaller device sizes while maintaining high performance across process, voltage, and temperature variations. A regulated cascode structure further minimizes the reference voltage variation. Post-layout simulations show a temperature coefficient (TC) of 34.6 ppm/oC between -40oC and 125oC while consuming 0.82 mW of power from a 1.8 V supply voltage. The proposed BGR demonstrates a power supply rejection ratio (PSRR) below -53.9 dB over the full frequency range and a noise spectral density of $16.5\mu {\text{V}}/\sqrt {Hz} $ at 10 Hz. The BGR is integrated with a low-dropout (LDO) voltage regulator, which combined have a chip area of 0.008316 mm2, offering reduced size compared to the present state-of-the-art untrimmed BGRs.

Multi-chip power module (MCPM) layout design automation has become an emerging research field in the power electronics society. MCPM physical design is currently a trial-and-error procedure that heavily relies on the designers' experience to produce a reliable solution. To push the boundary of energy efficiency and power density, novel packaging technologies are emerging with increasing design complexity. As this manual design process becomes the bottleneck in design productivity, the power electronics industry is calling for more intelligence in design CAD tools, especially for advanced packaging solutions with stacked substrates. This paper presents a physical design, synthesis, and optimization framework for 2D, 2.5D, and 3D power modules. Generic, scalable, and efficient physical design algorithms are implemented with optimization metaheuristics to solve the hierarchical layout synthesis problem. Corner stitching data structure and hierarchical constraint graph evaluation have been customized to better align with power electronics design considerations. A complete layout synthesis process is demonstrated for both 2D and 3D power module examples. Further, electro-thermal design optimization is carried out on a sample 3D MCPM layout using both exhaustive and evolutionary search methods. Our algorithm can generate 937 3D layouts in 56 s, resulting in 10 layouts on the Pareto-front. In addition, our optimized 3D layouts can achieve 1.3 nH loop inductance with 38 °C temperature rise and 836 mm2footprint area, compared to 2D layouts with 8.5 nH, 99 °C, and 2000 mm2.

A compact electro-thermal SiC Power MOSFET model implemented in LTSpice is presented in this paper. A 1200 V, 90A CREE SiC power MOSFET (C2M0025120D) has been used in this work to illustrate the parameter extraction and experimental model validation. The dynamic validation has been shown using a double-pulse test circuit. The convergence has been tested with the 4-switch topology of an inverter and a comparison between MAST, Verilog-A and CREE's empirical model of the same device has also been presented.

A novel algorithm for automatic behavioral model topology formulation (MTF) is described in this paper. Several new terms are defined to support this formulation approach. The algorithms for determining the controllability and equivalence of branches are developed. The identification of differential pairs and current mirror structures is implemented automatically. Some other algorithms identify a subset of nodes in circuits that are extracted and modeled, while the other nodes will be collapsed. The MTF algorithm then is applied to construct a new signal-path graph, i.e., forming an equivalent circuit that has the ability to represent the behavior of the original circuit in a much-simplified form. This algorithm is implemented in a fully automated modeling tool, ASCEND, which starts from the netlist description of a circuit and generates a differential-algebraic-equation-based model. These models are able to represent static and dynamic behaviors with excellent accuracy and significant simulation speedup. The details of the MTF algorithm are described. Examples of applying the MTF algorithm for behavioral modeling are given.

We investigate, for the first time, the design and implementation of a variable gain amplifier (VGA) circuit suitable for cryogenic temperature applications. Temperature compensation is studied to allow for such a large temperature swing. The proposed circuit is capable of operating at temperatures as low as 43 K. The device is fabricated in IBM silicon-germanium (SiGe) BiCMOS 5AM technology.

This paper presents a new approach for identifying nonlinear dynamic behaviour in analogue circuits. The approach facilitates the creation of models that more accurately reflect the dynamic behaviour of a circuit. It has been used in a fully automated, behavioural modelling tool, Ascend, that starts from the netlist description of the circuit and generates differential algebraic equation (DAE) based behavioural models. The underlying modelling approach is overviewed to provide a context for this research. Some demonstrative test results illustrate the effectiveness of the new method.

An algorithm for determining when electrical circuit poles and zeros (i.e., roots) are topologically localized to a node or coupled-pair of nodes is described. Discovering this relationship provides insight to designers for circuit optimization, and is a basis upon which nonlinear dynamic behavioral models can be built. This root localization algorithm, the main contribution of this paper, facilitates the creation of models that more accurately reflect the distinctive behavior of a circuit. This is accomplished by identifying when poles and zeros can be modeled as localized effects whose values change with circuit operating conditions. The underlying modeling approach is described to provide a context for this research. The algorithm is illustrated through several examples.