Zaher S. Andraus

dblp:90/6103 · DBLP profile ↗
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5ranked-venue papers
3as first author
0since 2021 · last 2008
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 2 first-authorArtificial intelligence and machine learning · 2 · 1 first-authorTheory of computation · 2 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 100%
Theoretical computer science
1 paper
Automated reasoning and model checking · 100%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › hardware verification and test › formal verification
abstraction refinement
0.012004
Automatic abstraction and verification of verilog models · DAC 2004
Electronic design automation › hardware verification and test
formal verification
0.012004
Automatic abstraction and verification of verilog models · DAC 2004
Electronic design automation
hardware verification and test
0.012004
Automatic abstraction and verification of verilog models · DAC 2004
Automated reasoning and model checking
satisfiability
0.012004
AMUSE: a minimally-unsatisfiable subformula extractor · DAC 2004
Automated reasoning and model checking › satisfiability › unsatisfiable cores
unsatisfiable core extraction
0.012004
AMUSE: a minimally-unsatisfiable subformula extractor · DAC 2004
Electronic design automation › hardware verification and test › formal verification
equivalence checking
0.012004
Automatic abstraction and verification of verilog models · DAC 2004

Methods — techniques the papers use, named apart from their topics

sound abstraction · 0.0counterexample analysis · 0.0branching order variation · 0.0SAT solver conflict learning · 0.0
YearPublicationVenuePosition
2008 Reveal: A Formal Verification Tool for Verilog Designs
Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
LPAR1
2006 Refinement strategies for verification methods based on datapath abstraction
abstract
In this paper, we explore the application of counter-example-guided abstraction refinement (CEGAR) in the context of microprocessor correspondence checking. The approach utilizes automatic datapath abstraction augmented with automatic refinement based on 1) localization, 2) generalization, and 3) minimal unsatisfiable subset (MUS) extraction. We introduce several refinement strategies and empirically evaluate their effectiveness on a set of microprocessor benchmarks. The data suggest that localization, generalization, and MUS extraction from both the abstract and concrete models are essential for effective verification. Additionally, refinement tends to converge faster when multiple MUses are extracted in each iteration.
Zaher S. Andraus, Mark H. Liffiton, Karem A. Sakallah
ASP-DAC1
2005 A Branch-and-Bound Algorithm for Extracting Smallest Minimal Unsatisfiable Formulas
Maher N. Mneimneh, Inês Lynce, Zaher S. Andraus, João Marques-Silva 0001, Karem A. Sakallah
SAT3
2004 Automatic abstraction and verification of verilog models
abstract
Abstraction plays a critical role in verifying complex sys-tems. A number of languages have been proposed to model hardware systems by, primarily, abstracting away their wide datapaths while keeping the low-level details of their control logic. This leads to a significant reduction in the size of the state space and makes it possible to verify intricate control interactions formally. These languages, however, require that the abstraction be done manually, a tedious and error-prone process. In this paper we describe Vapor, a tool that auto-matically abstracts behavioral RTL Verilog to the CLU lan-guage used by the UCLID system. Vapor performs a sound abstraction with emphasis on minimizing false errors. Our method is fast, systematic, and complements UCLID by serving as a back-end for dealing with UCLID counterexamples. Preliminary results show the feasibility of automatic abstraction and its utility in formal verification.
Zaher S. Andraus, Karem A. Sakallah
DAC1
2004 AMUSE: a minimally-unsatisfiable subformula extractor
abstract
This paper describes a new algorithm for extracting unsatisfiable subformulas from a given unsatisfiable CNF formula. Such unsatisfiable cores can be very helpful in diagnosing the causes of infeasibility in large systems. Our algorithm is unique in that it adapts the learning process of a modern SAT solver to identify unsatisfiable subformulas rather than search for satisfying assignments. Compared to existing approaches, this method can be viewed as a bottom-up core extraction procedure which can be very competitive when the core sizes are much smaller than the original formula size. Repeated runs of the algorithm with different branching orders yield different cores. We present experimental results on a suite of large automotive benchmarks showing the performance of the algorithm and highlighting its ability to locate not just one but several cores.
Yoonna Oh, Maher N. Mneimneh, Zaher S. Andraus, Karem A. Sakallah, Igor L. Markov
DAC3