A layout approach is described dedicatedly for MMICs, in which layout elements are transistors, inductors, capacitors, resistors, coplanar-waveguides, etc., implemented by GaAs fabrication process. The layout issue typical of such MMICs consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orientating constraints as well as shaping variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is effectively applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

A layout approach for monolithic microwave integrated circuits (MMICs) is described, in which layout elements are transistors, inductors, capacitors, resistors, coplanar waveguides, etc., implemented in a GaAs fabrication process. The layout issue typical of such MMIC's consists essentially in how to realize a single-layered placement of different shapes of layout elements under a variety of spacing and orienting constraints as well as shape variations. In this paper, the interconnection requirements among the elements are represented by a graph, to which a planarization algorithm is applied. On the basis of the planarization result, the physical placement is first constructed with the use of a merging scheme and then refined iteratively by means of a new rectangle-packing algorithm. Experimental results are also shown to demonstrate the practicability of the described layout approach.

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