This paper presents a multi-language test planning system, which is based on a goal-tree based test methodology. Multi-language support is achieved by adding a common abstraction layer on the top of different language specific details. The effectiveness of this strategy is demonstrated by using this tool for testing VHDL and SystemC models of a GSM system.

This paper presents a high-level test planning system for validating DSP real number models. It uses a goal tree structure as a framework of test planning and documenting. The goal tree based test plans are linked to the test bench generator, which creates test benches for simulation. The simulation results are checked and fed back to the test plans and new test benches are created accordingly. A GUI-based integrated software system has been developed for test planning and test automation based on this methodology. To illustrate this methodology, this paper uses the Synthetic Aperture Radar system as a case study. Finally, completeness and effectiveness of the generated test set are evaluated using structural approaches. Results of test set compaction are also presented.

Generation of test benches for large DSP behavioral models is a complicated, labor intensive task. Also, tests generated manually satisfy no formal definition of completeness. To address these needs, high level approaches to test bench development are employed which relieve the modeler of the details of this task. CASE tools are used to develop the test bench VHDL code, i.e., state machine behavior is specified with Ilogix Express VHDL and sensor behavior with Comdisco SPW. An intelligent interface prompts the user for high level test bench information, and inserts this information into the test bench code. The intelligent interface also allows the user to specify and control file I/O as a data source. Conceptually speaking, two approaches are being explored: (1) behavioral-the CASE tools develop complete high level models of the test bench, and (2) structural-a library of primitive components is developed so that a conventional schematic capture tool, e.g., Synopsys Graphical Environment, can be used to construct the test bench.

A behavioral test generation algorithm (called the B-algorithm) is presented which generates tests directly from behavioral VHDL circuit descriptions using three types of behavioral faults (behavioral stuck-at faults, behavioral stuck-open faults, and micro-operation faults). Behavioral faults are defined by perturbing VHDL constructs. In particular, behavioral stuck-at faults are defined for virtual signals corresponding to expressions as well as for normal signals. The B-algorithm generates tests using three basic test generation operations (activation, propagation, and justification), which are systematically executed by manipulating three data structures (B-frontier, J-frontier, and A-queue). Rules for the test generation operations are defined using the concepts of two-phase activation and two-phase propagation. The B-algorithm has two unique features. First, it can generate tests for behavioral stuck-open faults, which in fact can detect some gate level transition faults. Second, it incorporates the concept of two-phase testing, a testing strategy where a fault is detected using two consecutive test sequences.

A CAD tool, TIMESPEC, developed for solving the timing distribution problem of allocating realistic delays to the internal primitives (RTL models) of a digital device by using the linear programming approach is described. The inconsistencies in the manufacturer's specifications are also detected and corrected. TIMESPEC allows the use of embedded timing in behavioral VHDL models, and thus the end-to-end delays for all paths in the digital device are made available. An interface is provided with an X Windows based graphical tool, the Modeler's Assistant, which allows enumeration of all the input-to-output paths in the device. Thus a CAD tool is made available to system or chip designers/modelers for building accurate and synthesizable VHDL models.>

This paper presents two tools which facilitate the fault simulation of behavioral models described using VHDL. The first tool is the Behavioral Fault Mapper (BFM). The BFM algorithm accepts a fault-free VHDL model and a fault list of N faults from which it produces N faulty models. The process of mapping the faults in the fault list onto copies of the original VHDL model is automated. The N faulty models are immediately suitable for fault simulation. The second tool presented is the Test Bench Generator (TBG). The TBG algorithm creates the VHDL TestBench and all other files necessary to complete a batch-mode fault simulation of the N faulty models.

The coding of behavioral models is a time consuming and error prone process. In this paper the authors describe automated assists to the behavioral modeling process which reduce the coding time and result in models which have a well defined structure making it easier to insure their accuracy. The approach uses a particular graphical representation for the model. An interactive tool then assists in converting the graphical representation to the behavioral HDL code. The authors discuss a pictorial representation for VHDL behavioral models. In VHDL an architectural body is used to define the behavior of a device. These architectural bodies are a set of concurrently running process. These processes are either process blocks or various forms of the signal assignment statements. One can give a pictorial representation to a behavioral architectural body by means of a process model graph (PMG).>

A testable diagnosis array (TDA) is proposed for carrying out system-level fault diagnosis (based on the PMC model) centrally and in a non-hard-core manner. This diagnostics device is constructed with simple reliable logic cells. A characterization of t-TDA-diagnosable systems, based on an algebraic relationship between the testing graph T/sub n/ of a system of n component and its corresponding TDA, is given. It is shown that the TDA performs the diagnosis correctly and reaches its stable state in a number of clock periods related to the t-diagnostic diameter of T. A special class of t-TDA-diagnosable systems is defined, and an example from that class is used to illustrate the diagnosability of a system using a TDA.>

An algorithm is given for generating tests from chip-level functional descriptions. The algorithm uses a chip-level fault model to define faults and fault sensitization requirements, and uses the hardware description language (HDL) definition to solve for the test vector. Artificial intelligence techniques of goal trees and rule databases are use to implement the algorithm in ProLog. The goal types and solving strategies are outlined. The current, partial ProLog implementation is discussed.

Functional fault modeling and simulation for VLSI devices is described(*). A functional fault list is compiled using model perturbation and mapping of circuit defects into functional faults. A set of test vectors is then derived which detects all faults in the functional fault list. This same test vector set is then applied to a gate level model of the device. For the test case analyzed, a very high level of equivalent gate coverage was achieved. Conclusions are drawn as to the effectiveness of the technique and how amenable it is to automation.

The advent of Very Large Scale Integration (VLSI) technology has rendered the gate level model impractical for many simulation activities critical to the design automation process. As an alternative, an approach to the modeling of VLSI devices at the chip level is described, including the specification of modeling language constructs important to the modeling process. A model structure is presented in which models of LSI devices are constructed as single entities. The modeling structure is two layered. The functional layer in this structure is used to model the input/output response of the LSI chip. A second layer, the fault mapping layer, is added, if fault simulations are required, in order to map the effects of hardware faults onto the functional layer. Modeling examples for each layer are presented. Fault modeling at the chip level is described. Approaches to realistic functional fault selection and defining fault coverage for functional faults are given. Application of the modeling techniques to single chip and bit slice microprocessors is discussed.

Fault- tolerant characteristics of a Boolean n cube array of microprocessors are analyzed. Connectivity properties of the network graph are used to show that n processor or link failures are required to isolate a processor. For processor failures the network is shown to be n (one step) diagnosable. A testing algorithm is presented which can diagnose up to n processor failures.

An efficient method for representing multivalued functions is described. The method employs an algorithm which generates an efficient cover for a given function "directly," i.e., without resorting to the intermediate step of creating a table of prime implicants. Data are presented to show that the covers generated are as efficient in terms of cover size as prime implicant based methods. More importantly, however, the direct cover method is shown to require much less computation time than prime implicant based methods, thus making it practical for functions with a large number of input variables and/or as the radix of implementation increases. The algorithm is introduced by applying it to functional representations employing the traditional max and min operation. Next, a modified form of the algorithm is presented for use with the sum and product operators more appropriate to I2L and other current summation technologies.

A design procedure is presented for realizing multiple-valued sequential logic functions as tree structured networks of sequential universal logic modules (SULM's). Both definite and nondefinite finite state machines can be realized using this approach. The SULM employed is a multiple-valued multiplexer-flip-flop cascade that can be efficiently implemented in multiple-valued technologies.

The complexity of computational circuits versus radix is analyzed. Necessary and sufficient conditions are given that ensure that the complexity of certain computational circuits will be a monotonically decreasing function of radix. Mechanizations of a higher radix ripple carry adder, look-ahead adder, magnitude comparator, and parallel multiplier are given. Each mechanization is implemented using both I2L threshold logic and standard multiple-valued logic primitives and then tested against the necessary and sufficient conditions previously developed. A comparison is made of the relative effectiveness of I2L threshold logic versus logic primitives in realizing computational circuits whose complexity is a decreasing function of radix.

The design of a graphic display system for remote terminal application is presented. Control data requirements are reduced by generating a useful set of graphic primitives locally at the remote terminals.