The authors describe a synthesis approach that maps a behavioral finite state machine (FSM) description into a testable gate-level structure. The term testable, besides implying the existence of tests, also means that the application of test patterns is facilitated. Depending on the test strategy, the state registers of the FSM are modified, e.g. as scan path or self-test registers. The additional functionality of these state registers is utilized in system mode by interpreting them as smart state registers, capable of producing certain state transitions on their own. To make the best use of such registers, the authors propose a novel state encoding strategy based on an analytic formulation of the coding constraint satisfaction problem as a quadratic assignment problem. An additional minimization potential can be exploited by appropriately choosing the pattern generator for self-testable designs. Experimental results indicate that, compared with conventional design for testability approaches, significant savings are possible this way.>

Conventionallyself-test hardware is added after synthesis is completed.For highly sequential circuits like controllers this design method either leads to high hardware overheads or compromises fault coverage.In this paper we outline a unified approach for considering self-test hardware like pattern generators and signature registers during synthesis.Three novel target structures are present@ and a method for designing parallel self-testable circuits is discussed in more detail.For a collection of benchmark circuits we show that hardware overheads for self-testable circuits can be significantly reduced this way without sacriilcing testability.

Combinational functions involving XOR-operations, e.g. Reed-Muller forms (RMFs) or parity functions, often yield area-inefficient realizations when standard synthesis algorithms are used. A specialized module generator targeted towards such functions was implemented. XPLAs, the resulting novel PLA-like structures for mixed polarity RMFs, are compared with conventional PLAs in order to assess whether the theoretical advantages of RMFs over sum-of-products representations can be transformed into practical benefits. It is shown that although testability is a definite plus of these structures, area considerations will probably restrict the use of RMF minimizers to special applications.>

Placement and related aspects of the BEAR macrocell layout system are described. A combination of top-down and bottom-up heuristics is used to make best use of a hierarchical description. The interdependency of placement and routing is considered explicitly. Experimental results show a considerable improvement over previous approaches.>

The authors present a novel state assignment technique for synchronous finite state machines (FSMs) that are implemented as single programmable logic arrays (PLAs) using Johnson counters as state memories. The goal is to minimize the number of product terms in the PLAs and thus the overall area of the FSMs. The authors use a three-step approach to achieve this. First, the FSM description is adapted to allow an optimal use of the computer properties; then the counter is embedded by ordering the internal states of the FSM; and finally the states are coded. The product term reductions obtained are, on the average 20% to 30% compared to conventional D-latch-based FSM implementations.>