Recent advancements have marked significant progress in photoacoustic imaging as an effective method for acquiring deep bio-tissue visuals in modern medical clinical therapy and the efficacy of U-Net and its variants has been established for imaging quality enhancement in this field. Unlike common computer vision datasets such as ImageNet [1] and PASCAL VOC [2], biomedical images exhibit highly structured patterns, low spatial resolution, and single-channel modality, as shown in Fig. 1. Additionally, the U-Net parameters trained for medical super-resolution tasks demonstrate a high sparsity ratio, making them suitable for implementation on edge-computing platforms. Therefore, developing an energy-efficient photoacoustic imaging setup in this area is a natural progression. However, this development is constrained by the current neural network architectures, which are built around a U-Net backbone. The multi-stage feature extractor, skip connection integration across different blocks, and the encoder-decoder backbone design pose significant challenges to cutting-edge computational hardware platforms. In this study, a scalable, sparsity-supported neural network accelerator architecture for bio-tissue imaging quality enhancement is proposed to meet the stringent requirements of latency and energy efficiency, as depicted in Fig. 2. This architecture achieves desired performance improvements by exploring the sparsity possibilities in neural network during the training process and implementing an end-to-end pixel-first hardware design to minimize data movement and support sparsity computation. Compared with the state-of-the-art related works, this optimized architecture has achieved minimum on-chip storage overhead and the fastest frame for the application of photoacoustic imaging quality enhancement. The scalable architecture has also been implemented on a Xilinx XCZU9EG FPGA and attains a performance of PSNR@ 24 dB and a frame rate of 164 fps at a working frequency of 250 MHz.

This paper presents a 1st-order extended-counting (EC) incremental analog-to-digital converter (IADC) based on dynamic amplifier (DA). The wide output swing and high gain requirement of the amplifier makes it infeasible to design an energy-efficient high-resolution EC IADC based on DA. Conventional gain-boosting methods, such as multi-stage and cascoding, suffer from the stability issue and limited output swing respectively. To solve this problem, a foreground gain calibration method is proposed for reducing the gain requirement by compensating the quantization error caused by the limited gain of DA. Additionally, a two-stage DA is proposed to achieve wide output swing and high energy-efficiency, which combines the floating-inverter-based amplifier (FIA) and the switched-inverter-based amplifier (SIA). SIA works as the 2nd stage, providing wide output swing while FIA as the 1st stage maintains the gain > 50 dB. A prototype of 1st-order EC IADC based on the proposed DA with gain calibration is fabricated in 180-nm CMOS technology. Operating under 1.8-V power supply, the EC IADC achieves a SNDR/DR of 94.6 dB/ 98.1 dB and 20μW power consumption at 921 kHz offs, leading to a Schreier figure-of-merit (FOMSNDR) of 174.1 dB.

In this work, a solid-state direct time-of-flight (dToF) and adaptive beam-steering Light Detection and Ranging (LiDAR) system is proposed for machine learning (ML) based object detection. To leverage the capabilities of software and hardware, a co-optimization design from a neural network based algorithm to the architecture of transmitter, receiver and optical components is realized. Firstly, an object detection neural network is proposed for the depth-only input algorithm, which indicates the Region of Interest (ROI) in the illuminating field and gives hints of opened scan channels in the next two frames to decrease the total cost of the laser driver and sensor array. Next, the proposed network utilizes the Cross-Stage-Patrial (CSP) block to replace the residual structure in the backbone to achieve a lightweight performance and is implemented on the NVIDIA-Jetson to verify the system-level adaptive beam steering feature. To realize the smart working mode, a customized multi-channel and addressable TX is designed for adaptive and optical control to save power consumption and extend the ranging distance. At the same time, a 128×80 resolution RX which consists of Single-Photon Avalanche Diodes (SPADs) and column-wise Time-to-Digital Converter (TDC) is incorporated to capture the returned photons for combining sub-regions into an entire depth map. Next, to customize the specific scanning mechanism, for the optical setup, a cylindrical lens array is designed to reshape the laser beam, which matches the pattern of the transmitter to illuminate different targeted objects. Both the laser driver chip and the sensor chip with a 128×80 SPAD array are fabricated in the 180-nm Bipolar-CMOS-DMOS (BCD) process. Finally, the laser driver chip realizes the power of 5 W with an adjustable pulse width of 1.5 ns and the SPAD array integrates the depth accuracy of 5 cm at 15 m. Due to that the neural network realizes an accuracy up to 0.8, a low-power solid-state LiDAR prototype with adaptive beam steering is demonstrated.

The conversion accuracy of successive approximation register (SAR) analog-to-digital converter (ADC) is mainly affected by the capacitor mismatch. In this brief, a histogram-based calibration technique is proposed, which does not require any additional analog circuitry. In this work, the method of partial fitting is used to detect irregular code densities, and construct a cost function to update the weight recursively. The prototype of the calibration is verified with a 12-bit SAR ADC manufactured in 28-nm standard CMOS process. At the sampling rate 50 MS/s, the measurement results indicate that the maximum spurious-free dynamic range (SFDR) can be improved from 77.26 to 88.26 dB, using 10.6 fJ/conversion-step, including reference voltage buffer, with a low-frequency input signal.

Silicon photodetectors, such as photodiode (PD), are extensively used in optical sensing as their proper performance and low cost to achieve screen brightness adjustment, ambient light flicker detection, and other functions. With the rise of under-screen optical sensing, PD is no longer sufficient for low-light level light detection and real-time low light level flicker detection. While an emerging detector, single photon avalanche diode (SPAD), shows its advantage to ultralow light sensing. However, SPAD tends to saturate at high light levels, which limits its widespread application. To inspire ambient light sensor design and address these issues, this paper proposes a high sample per second (SPS), wide dynamic range (DR) and ultralow illuminance detection SPAD array system on chip (SoC). A$16\times 16$SPAD array architecture along with counter and charge-pump is designed in 180nm BCD process to sense 100μdux ambient light at 660nm. On-chip FFT processor of 2048 points with 32-bit accuracy is realized to process sampled optical waveform for flicker detection. Besides, an area-efficient integrated charge pump is implemented to regulate high-voltage (19~25V) to SPADs with on-chip digital auto-gain control (AGC), which improves the optical DR from 87db to 123db. This work extends the optical sensing range significantly and demonstrates the effectiveness of the proposed SoC with systematical measurements.

A high-speed low-noise comparator with an auxiliary inverter-based (AIB) preamplifier is proposed in this brief. The preamplifier adopts an inverter-based input pair without tail transistors, which is well-suitable for low-supply-voltage applications, especially in deep submicrometer technologies. Moreover, it achieves high bandwidth and low noise with high current efficiency. Dynamic common-mode feedback combined with a secondary inverter-based input pair regulates the output common-mode (CM) voltage of the preamplifier by itself against PVT and input CM voltage sensitivity without complex control logic and quiescent current. Embedded in a 200 MS/s 16-bit successive-approximation-register (SAR) analog-to-digital converter (ADC) in standard 28-nm CMOS technology, the proposed comparator achieves a 68.1-ps delay at a 50-$\mu \text{V}$differential input voltage and a root-mean-square input-referred noise of 45.6$\mu \text{V}_{\mathrm {rms}}$under the 1-V power supply.

To minimize the area of analog-to-digital converters (ADCs) for multichannel applications and break the SNDR limitation caused by DAC-induced nonlinearity, a more area-efficient mismatch error shaping (MES) scheme is proposed in noise shaping (NS) successive-approximation (SAR) ADC. By employing a switched-capacitor (SC) voltage divider, the proposed method makes the flash ADC and data weighted averaging (DWA) digital circuits in the original MES method obsolete. Therefore, the complexity of the architecture is highly reduced, and the area is significantly reduced to 0.037 mm2. In addition, the power consumption for the MES implementation is significantly decreased by more than 7.3%. The proposed SAR ADC is fabricated in GF 40-nm CMOS technology. The measurements show that the proposed MES technique improves the SFDR from 64 to 102 dB and decreases the THD from -63.6 to -95.7 dB. The SNR and SNDR in a 20-kHz bandwidth are 91.6 and 90.2 dB, respectively. The power consumption is 383.4 μW with a 1.1-V power supply at a 16-MS/s sampling rate.

This brief presents a background calibration technique for pipelined successive-approximation-register (pipelined SAR) analog-to-digital converters (ADCs), which resolves the errors from capacitor mismatches and inaccurate interstage gain errors. The dither signal is injected in the capacitor digital-to-analog converter (DAC), while its residue voltage increment is neutralized through paired comparators with opposite polarity offsets, thereby relaxing the design requirement of the residue amplifier. While one of the comparators is generating the residue signal, the other one is detecting the signal range and helping to obtain the bit weights. This brief also introduces the circuit design of paired comparators with opposite offsets. The background calibration technique is verified in a 5b + 8b pipelined SAR ADC. Simulation results show that the spurious-free dynamic range (SFDR) and the signal-to-noise and distortion ratio (SNDR) are improved from 54.5 to 94 dB and 49 to 68.9 dB, respectively. The mean value of the voltage swing increment is 34 mV with noise sources, offset, gain error, and capacitor mismatches.

This paper presents a linearity-enhanced 10-bit 160-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with a high-speed and low-noise comparator. A p-well floating technique for linearity improvement of sampling switch is proposed. The total parasitic capacitance of the sampling switch is depressed compared to conventional structures. Also, the variation of parasitic capacitance is reduced. Furthermore, a substrate voltage boosting technique is proposed to depress the noise of comparator at a high conversion rate. In addition, an improved parallel SAR logic is exhibited to increase the speed of SAR feedback loop and enhance the settling of digital-to-analog converter (DAC). Last, an adaptive sampling technique is utilized to increase the sampling time of SAR ADC. The proposed SAR ADC is fabricated in the 65-nm CMOS process, consuming 2 mW at a 1.2-V power supply. It achieves a signal-to-noise distortion ratio (SNDR) >55.6 dB and spurious-free dynamic range (SFDR) >69 dB at 160 MS/s. The ADC core occupies an active area of 0.023 mm2, and the corresponding figure-of-merit (FoM) is 25.4 fJ/conversion-step at Nyquist input.

This paper presents a 10-bit 1-GS/s four-channel time-interleaved (TI) successive approximation register (SAR) analog-to-digital converter (ADC). To suppress the time skew, the full rate master clock-based sampling technique is adopted. The effect of sampling switch mismatches on time skew is addressed. The measured time skew spurs caused by the sampling switch mismatches are around -52 to -55 dB at Nyquist input. Then, a tap-interpolating fractional delay filters-based digital background time skew calibration technique is proposed. Also, a full analysis of the effects of the various parameters on the time skew generated spur levels is presented, which indicates that the time skew error level is related to the length of calibration filters, calibration range, and bandwidth penalty. The subchannel ADC exploits a 250-MS/s SAR ADC with a low-cost high-speed subradix-2 searching technique. The reference interference of nonbinary TI ADCs is discussed and tolerated by the subradix-2 searching scheme. The proposed adders-based encoding circuit is optimized with lower propagation delay to meet high-speed requirements. The prototype was fabricated in a 65-nm CMOS technology. The measurement results show that the ADC achieves a signal-to-noise-plus-distortion ratio of 49.6 dB with a power of 15.95 mW and a figure of merit of 63 fJ/conversion step when operating at 1-GS/s and 458.1-MHz Nyquist input. The ADC core achieves an area of 0.158 mm2.

This live demonstration presents a first-in-kind fully integrated Ku-band Synthetic Aperture Radar (SAR) transceiver chip in 65-nm CMOS that fits for micro-UAVs. The transmitter presents 13.3-dBm output power and 1.48 GHz chirp bandwidth centering at 15 GHz. The receiver front-end attains 23.5-dB gain, -33-dBm IPldB and 5.6-to-6.3dB noise figure. The receiver analog baseband achieves 0.68-to-9.8-MHz programmable passband and 55-dB variable gain range. The integrated ADC has 9.4-bit ENOB. The SAR chip achieves super-resolution of 11.2 cm and consumes only 260-mW power. The ranging and imaging functions of the prototype are showcased.

This brief presents a low-computational, flexible nonbinary searching technique for high-speed successive approximation register (SAR) analog-to-digital converters (ADCs). By embedding the redundant weights into each capacitor branch of digital-to-analog converter (DAC) array, the conventional binary DAC array is customized as a nonbinary DAC array without additional control logics, resulting in fast conversion and negligible overhead. The weight of each branch could be defined flexibly with certain constraints, which is derived in this brief. Moreover, the nonbinary output codes are encoded to binary codes by adder-based encoding logics that show far less power and area penalty. To demonstrate the proposed nonbinary searching technique, a 10-bit 280-MS/s high-speed SAR-ADC is presented, which achieved an signal-to-noise-distortion ratio of 52.4 dB and a figure of merit of 21 fJ/conversion step.

In this paper, a digital time skew calibration technique for time-interleaved (TI) ADCs is presented. The time skew calibration for TI-ADCs in analog domain suffers from limited correction accuracy and additional jitter. And the proposed digital time skew calibration method estimates the polarity of the time skew through correlation of adjacent channels and corrects the time error by adopting adaptive fractional delay filters iteratively. Simulation results show that, in a 4-channel 1GS/s 12-bit TI-ADC system, the SFDR can be improved to 78dB by 5-order FIR filters within a calibration range of [-0.005/fs, +0.005/fs].

In this paper, a statistic based time skew calibration method for time-interleaved ADCs is presented. By comparing the mean value of the multiplication of signals in two adjacent channels, the time skew can be estimated. Subsequently, a capacitor array based digitally controlled delay block placed in sampling clock path is adopted to compensate the time skew. In addition, the precision of calibration is further improved through using a monotonic small capacitor array. In a 4-channel 1GS/s 12-bit TI-ADC system, the spurious free dynamic range (SFDR) can be improved to 77.5dB with 0.25ps LSB in the digitally controlled delay block.

This paper proposes a frequency-interleaved ADC (FI-ADC) architecture, which can avoid time skew problem existing in time-interleaved ADC (TI-ADC). The analysis filter bank of the FI-ADC is implemented by low order analog filters and can be integrated easily. In addition, prototype of an 8-channel 2GS/s 12-bit FI-ADC is designed. Based on the spurious-free dynamic range (SFDR), the comparison of variation of analog filter coefficients in FI-ADC and time skew in TI-ADC is done. Simulation results show that FI-ADC is more suitable for GHz implementation, and the proposed FI-ADC has a better gain mismatch tolerance than TI-ADC.