In today's competitive market, a company's success is strongly dependent on delivering sophisticated and state-of-the-art IPs prior to their competitors. To take a short cut, a company may resort to reverse engineering or pirating their competitor's IP.

In the last decade, OpenCL has sparked the interest of the computing world as it is a language based on an open standard that can run on many different heterogeneous platforms. This standard is continuously evolving to adapt to various use cases of different platforms. For example, with requests from the FPGA community, the pipe construct was added to the standard to facilitate the implementation of streaming applications. The versatility of the pipe construct allows several different usage modes. In this paper, we explore various implementations of pipes to evaluate the pipe construct. Our results show that for the FIFO mode, an implementation using an off-the-shelf component is favourable due to its performance and resource usage. However for the remaining modes, our proposed pipe implementation performs significantly better than other implementations at a resource utilization cost that is insignificant when compared to the abundance of resources in modern FPGAs.

Field Programmable Gate Arrays (FPGAs) are an ideal platform for building systems with custom hardware accelerators, however managing these systems is still a major challenge. The OpenCL standard has become accepted as a good programming model for managing heterogeneous platforms due to its rich constructs. Although commercial OpenCL frameworks are now emerging, there is a need for an open-source OpenCL framework that facilitates the exploration of the overall system architecture and software, as well as the implementation and architectures of the custom hardware accelerators (devices). In this paper, we use an OpenCL framework to compare interconnect implementations for a simple multiprocessor accelerator.

Much like other computing platforms in the world today, FPGAs are becoming increasingly larger and contain large amounts of reconfigurable logic. This makes FPGAs an acceptable platform for multiprocessor systems. However in today's world of FPGA computing, very limited infrastructure is available to facilitate the creation of cache coherent shared memory systems for FPGAs. This paper introduces FCache, a system for shared memory cache coherent processing on FPGAs. The paper also describes the mapping of the conventional shared bus to FPGAs using two distinct network implemented in FCache. FCache also provides flushing and multithreaded synchronization functionalities, such as locking and unlocking of a mutex variable, which is embedded in its cache component. Despite these additional functionalities, results show that FCache has little resource overhead compared to a previous more simplistic cache coherent system that was targeted for FPGAs.

Modern FPGAs have the ability to place many processing elements on a single die that can access shared memory. In a multiprocessing system, mutex variables are often used to provide proper synchronization and access to memory locations shared by the processing elements. This paper introduces a novel technique to manage mutex variables in caches for FPGAs, and is compared to an off-the-shelf system built mostly by components from an FPGA vendor. Results show that a cache-coherent system using our proposed technique performs more barriers per second than the off-the-shelf system with comparable hardware resources while also providing coherent caches.