This high-speed and power-efficient content addressable memory employs parallel lookups to expedite matching without compromising power consumption. It introduces three significant innovations: i. pre-computation based operation, which enhances search speed by eliminating mismatch conditions only in 4-bit comparisons; ii. a hybrid match line structure that strategically balances power and delay, amalgamating the high-speed attributes of NOR with the low-power characteristics of NAND; and iii. a control technique that processes segments to the final match line. Performance metrics exhibit significant enhancements when these methodologies are seamlessly integrated. Employing 45 nm CMOS technology, the design accommodates diverse process voltages, temperatures, and frequencies for a$64\times 32$memory array. Monte Carlo simulations validate design stability. The proposed architecture surpasses the leading benchmark in speed and power-delay-product by 62.85% and 99.78%, respectively. The proposed architecture supports repeated data searches at frequencies up to 2 GHz, which has the potential to revolutionize search in high-performance computing, mobile devices, and IoT applications.

Content-addressable memory (CAM) is a hardware searchengine used for parallel lookup that assures high-speed match but at the cost of higher power consumption. Both low power NAND-type and highspeed NOR-type match-line (ML) schemes suffer from requirement of the precharge prior to the search. Recently, a precharge-free ML structure has been proposed but with inadequate search performance. In this brief, a self-controlled precharge-free CAM (SCPF-CAM) structure is proposed for high-speed applications. The proposed architecture is useful in applications where search time is very crucial to design larger word lengths. The proposed 128×32-bit SCPF-CAM structure has been implemented using predictive 45-nm CMOS process and simulated in SPECTRE at the supply voltage of 1 V. The ML delay using the proposed SCPF-CAM architecture has been reduced by 88% and 73% compared to the precharge-free and traditional NAND-type ML structure.

A ternary content addressable memory (TCAM) speeds up the search process in the memory by searching through prestored contents rather than addresses. The additional don't care (X) state makes the TCAM suitable for many network applications but the large amount of cell requirement for storage consumes high power and takes a large design area. This paper presents a novel architecture of TCAM, which prestores 2 bits of data in an up-down manner and provides multiple masking operations through a single control multimasking circuit. The proposed dual bit associative memory with match error and mask control (EMDBAM) consumes low power and selects the valid value on matchline through match error controller. The proposed design has been implemented using a standard 45-nm CMOS technology, and the extracted layout has been simulated using SPECTRE with the supply voltage at 1 V. The proposed EMDBAM can reduce the cell area by 39% compared with a basic TCAM design with a reduction of 9.6% in the energy-delay product.

In this paper, a hybrid 1-bit full adder design employing both complementary metal–oxide–semiconductor (CMOS) logic and transmission gate logic is reported. The design was first implemented for 1 bit and then extended for 32 bit also. The circuit was implemented using Cadence Virtuoso tools in 180-and 90-nm technology. Performance parameters such as power, delay, and layout area were compared with the existing designs such as complementary pass-transistor logic, transmission gate adder, transmission function adder, hybrid pass-logic with static CMOS output drive full adder, and so on. For 1.8-V supply at 180-nm technology, the average power consumption (4.1563$\mu $W) was found to be extremely low with moderately low delay (224 ps) resulting from the deliberate incorporation of very weak CMOS inverters coupled with strong transmission gates. Corresponding values of the same were 1.17664$\mu $W and 91.3 ps at 90-nm technology operating at 1.2-V supply voltage. The design was further extended for implementing 32-bit full adder also, and was found to be working efficiently with only 5.578-ns (2.45-ns) delay and 112.79-$\mu $W (53.36-$\mu $W) power at 180-nm (90-nm) technology for 1.8-V (1.2-V) supply voltage. In comparison with the existing full adder designs, the present implementation was found to offer significant improvement in terms of power and speed.