Traditionally, conflict resolution in an input- buffered switch is solved by finding a matching between inputs and outputs per time slot, which incurs unscalable computation and communication overheads. The main objective of this paper is to propose a scalable solution, called the mailbox switch, that solves the out-of-sequence problem in the two-stage switch architecture. The key idea of the mailbox switch is to use a set of symmetric connection patterns to create a feedback path for packet departure times. With the information of packet departure times, the mailbox switch can schedule packets so that they depart in the order of their arrivals. Despite the simplicity of the mailbox switch, we show via both the theoretical models and simulations that the throughput of the mailbox switch can be as high as 75%. With limited resequencing delay, a modified version of the mailbox switch achieves 95% throughput. We also propose a recursive way to construct the switch fabrics for the set of symmetric connection patterns. If the number of inputs, N, is a power of 2, we show that the switch fabric for the mailbox switch can be built with y log2 N 2 x 2 switches.

Load-balanced switches have received a great deal of attention recently as they are much more scalable than other existing switch architectures in the literature. However, as there exist multiple paths for flows of packets to traverse through load-balanced switches, packets in such switches may be delivered out of order. In this paper, we propose a new switch architecture, called the CR switch, that not only delivers packets in order but also guarantees 100% throughput. The key idea, as in a multiple access channel, is to operate the CR switch in two modes: (i) the contention mode in light traffic and (ii) the reservation mode in heavy traffic. To do this, we invent a new buffer management scheme, called I-VOQ (virtual output queue with insertion). With the I-VOQ scheme, we give rigorous mathematical proofs for 100% throughput and in order packet delivery of the CR switch. By computer simulations, we also demonstrate that the average packet delay of the CR switch is considerably lower than other schemes in the literature, including the uniform frame spreading scheme (Keslassy et al., 2003), the padded frame scheme (Jaramillo et al., 2006) and the mailbox switch (Chang et al., 2004).

Many switch architectures with buffers placed at input ports suffer from the head-of-line blocking (HOL) problem and thus can not achieve 100% throughput. For an input-buffered switch, the number of HOL packets is often characterized by the Lindley equation for a discrete-time queue, i.e. q(t+1)=(q(t)-F)/sup +/+a(t), where q(t) is the number of HOL packets at time t, a(t) is the number of new HOL packets at time t, and F is the maximum number of HOL packets that can depart per unit of time. As the total number of HOL packets is bounded in a switch, it places an upper limit on the expected number of HOL packets. Thus, the maximum throughput is the utilization that makes the expected HOL packets equal to the upper limit. For the case with F=1, the expected number of HOL packets can be found via the Pollaczek-Khinchin formula and the maximum throughput can be solved by a quadratic equation as reported in [M.J. Karol et al. (1987), C. Kolias et al. (1996), G. Thomas (1997)]. One of the main contributions of this paper is that we derive a generalized Pollaczek-Khinchin formula for the case F>1. Such a formula is then used for finding the maximum throughput of several input-buffered switches. For the case F/spl Gt/1, numerical computation of the maximum throughput becomes difficult. For large F, we present several bounds and approximations for the throughput. Numerical studies and simulation results confirm that our approximation methods work well.