Artificial Intelligence has recently become a major trend, driving the rapid development of new compute capabilities. As AI functionality has improved, the demand for even greater capabilities has grown, requiring significantly higher levels of performance and energy-efficiency in the IT infrastructure. The maturation of classical semiconductor scaling has made delivering these higher levels much more challenging; reliance on scaling alone is insufficient. As a result, innovations in design, design automation, and architecture are crucial to improving power-performance. Accelerators in heterogeneous systems will increasingly be needed to improve overall system capabilities and power/performance. To enable practical accelerator integration, system architectures must be designed to easily incorporate heterogeneous components such as today's GPUs, as well as future accelerators for cognitive applications. Design processes must increase in efficiency to enable the cost-effective design of application-specific accelerators. In this presentation, I will describe these trends, some exemplary innovations that address them, and areas of future research towards heterogeneous systems for the AI era.

This paper is a tutorial-style introduction to a special session on: Effective Voltage Scaling in the Late CMOS Era. It covers the fundamental challenges and associated solution strategies in pursuing very low voltage (VLV) designs. We discuss the performance and system reliability constraints that are key impediments to VLV. The associated trade-offs across power, performance and reliability are helpful in inferring the optimal operational voltage-frequency point. This work was performed under the auspices of an ongoing DARPA program (named PERFECT) that is focused on maximizing system-level energy efficiency.

Technology scaling has provided the semiconductor industry a recipe to successfully meet the application demands for performance for over three decades. This computational capacity was further fueled by the success of circuit and architecture-level innovation, which provided performance improvement in each processor generation. However, future processor designs face a number of key challenges in sustaining the growth trends. The dawn of the 22nm node, and beyond, marks an era of new trends and challenges; where the cost and complexity associated with each technology node is increasing at much faster rate than the device performance gains. Novel tools and design methodologies are needed to not only compensate for these challenges but also to leverage emerging technologies to achieve the desired performance in future processor architectures. Technology alternatives such as 3D integration have attracted significant interest as an additional way of sustaining the density scaling and performance growth.

Given the exponential increase of fabrication costs, the global recession and credit crunch, one may ask if Moore's Law is financially viable beyond 22nm node. Can we justify the return-of-investment (ROI) for continuous scaling beyond 22nm? Shall we consider other alternatives for integration, such as silicon-in-a-package (SiP) or 3D integrations?