This brief presents an energy-efficient accelerator for convolutional neural network (CNN) layer computations in a compact system. The accelerator replaces traditional data shift registers with a multiplexer-based barrel shifter, offering greater flexibility for supporting various models and reducing power consumption by 56.2% compared to flip-flop-based shifters. The prototype, fabricated using a 180-nm CMOS process, accelerates CIFAR-10 dataset CNN computations by 8.5 times compared to a system without the accelerator. It achieves this speedup while consuming only$4.7 ~\mu \text{W}$of power and$9.53 ~\mu \text{J}$for each inference task.

The Internet of Things (IoT) is a rapidly evolving application space. One of the fascinating new fields in IoT research is mm-scale sensors, which make up the Internet of Tiny Things (IoT2). With their miniature size, these systems are poised to open up a myriad of new application domains. Enabled by the unique characteristics of cyber-physical systems and recent advances in low-power design and bare-die 3D chip stacking, mm-scale sensors are rapidly becoming a reality. In this paper, we will survey the challenges and solutions to 3D-stacked mm-scale design, highlighting low-power circuit issues ranging from low-power SRAM and miniature neural network accelerators to radio communication protocols and analog interfaces. We will discuss system-level challenges and illustrate several complete systems and their merging application spaces.

An ARM-based sensing platform powered entirely by small-scale benthic microbial fuel cells (MFCs) for oceanic sensing applications is presented. The ultra-low power chip featuring an ARM Cortex-M0 processor, 3kB of SRAM, and power management unit (PMU) with energy harvesting from MFCs is designed to consume 11nW in sleep mode for perpetual sensing operation. A small-scale micro-MFC with 21.3cm2anode surface area was connected to the on-chip PMU to charge a thin film battery of 1mAh capacity. A 49.3-hour long-term experiment with 8-min sleep interval and 1 sec wake-up time demonstrated the sustainability of chip-on-mud concept. During sleep mode, the system charges the 4V battery at 380nA from the micro-MFC generating 5.4μW of power, which can support up to 20mA of active mode current.

This paper proposes an energy-efficient VGA full-frame feature extraction processor design. It is based on the SURF algorithm and makes various algorithmic modifications to improve efficiency and reduce hardware overhead while maintaining extraction performance. Low clock frequency and deep parallelism derived from a one-sample-per-cycle matched-throughput architecture provide significantly larger room for voltage scaling and enables full-frame extraction. The proposed design consumes 4.7mW at 400mV and achieves 72% higher energy efficiency than prior work.

We present a self-adapting power management unit (PMU) for ultra-low power wireless sensor nodes. The PMU uses 1.03nF of on-chip MIM capacitance in a reconfigurable switched-capacitor network (SCN) that automatically adapts to different battery voltages for down-conversion and different harvesting sources/harvesting conditions for up-conversion. The PMU achieves 63.8% / 60.7% down-conversion efficiency at 17.9μW active mode / 12.8nW sleep mode power loading. With the adaptive down-conversion ratio, load power range is improved by 3.76× and 5.48× in sleep and active mode, respectively. We show how the proposed adaptation method enables harvesting with solar, microbial fuel cell, and thermal energy sources, increases harvesting efficiency by 1.92× and achieves the peak extraction efficiency of 99.8% for solar cell.

Designing an ultra-low power sensor node requires careful consideration of the system-level energy budget. Depending on applications, various components can dominate total energy. In this paper, we review three different system energy budget scenarios where any of the microprocessor, memory, and timer of a sensor node can dominate the energy budget. The design space and corresponding trade-offs for these three components are explored to suggest guidelines for the design of ultra-low power sensor nodes.

We propose an adaptive reliability enhancement structure for deeply-scaled CMOS and future devices that exhibit nondeterministic behavior. This structure forms the basis of a confidence-driven computing model that can be implemented in either a rollback recovery or an iterative dual modular redundancy method incorporating synchronous handshake schemes. The performance and cost of the computing model are estimated using a 45 nm CMOS technology and the functionality is verified by FPGA-based emulation. The confidence-driven computing model is demonstrated using a 16-bit, 12-stage CORDIC processor operating under random, transient errors. The confidence-driven computing model adapts to the fluctuating error rates at the device substrate level to guarantee the reliability of computation at the system level. This computing model costs 4.2 times smaller area and 2.7 times less energy overhead than triple modular redundancy to guarantee a system-level mean time to failure of two years.