Spiking neural networks (SNNs) have shown great potential in achieving high energy efficiency and low power consumption compared to artificial neural networks (ANNs). However, there remains a significant accuracy gap between SNNs and ANNs. To address this issue, we present an in-memory neuromorphic computing (IMNC) chip that supports hybrid spiking/artificial neural networks (S/ANNs) and sparsity-aware data flows. With the IMNC chip, we aim to improve inference accuracy while simultaneously achieving high energy efficiency through optimization at the algorithm, architecture, and circuit levels. First, at the algorithm level, we note that SNNs extract temporal features from input spikes using time-domain convolution operations. Based on this insight, we efficiently utilize leaky integrate (LI) neurons to hybridize SNNs and ANNs, thereby improving accuracy while maintaining highly sparse operations. Second, at the architecture level, we design a sparsity-aware architecture that supports a hybrid S/ANN topology with varying sparsity. Finally, at the circuit level, we propose a ring-based in-memory computing (IMC) macro, whose energy consumption is inversely proportional to the input sparsity, making it ideal for performing energy-efficient multiplication and accumulation (MAC) operations in both SNNs and ANNs. We evaluate the proposed hybrid S/ANNs on various classification tasks and demonstrate their stronger classification and generalization ability compared with pure SNNs. Notably, our IMNC chip, fabricated using 22 nm CMOS technology, achieves impressive measured accuracy rates of over 95% for voice activity detection (VAD) and ECG anomaly detection. Additionally, our IMNC chip demonstrates superior dynamic energy efficiency of 0.43 pJ per synaptic operation, outperforming related works.

This article presents a clock-free spiking neural network (SNN) intelligent inference engine (IIE) for artificial intelligence of things (AIoT) sensor nodes, which often operate in random-sparse-event (RSE) scenarios. The IIE drastically reduces the system’s long-term average (LTA) power consumption, improves energy efficiency, and achieves microsecond level inference latency. Three techniques are proposed: 1) A clock-free SNN architecture without clock tree, frame generator, and arbiter, is driven by the output spikes, which are encoded with level-crossing (LC) sampling method; the circuit activity is completely related to event activity and spike rates, dramatically reducing the overall power consumption and latency. 2) The bioinspired leaky-integrate-fire (LIF) neurons directly extract the time-domain information from asynchronous spikes, reducing the network size and number of operations. 3) The computing-in-memory (CIM) and mixed-signal synapse-neuron circuits are employed to increase the SNN parallelism and avoid weight movements, thus improving the energy efficiency and response speed. The measured LTA power is bounded at 82 nW while the event-driven chip is on call and waiting for events; the energy efficiency is 0.53 pJ per synapse operation (SOP), only 1/3 that of state-of-the-art methods at 4bit weights even with 180 nm technology. We demonstrate electrocardiogram (ECG) recognition as a typical AIoT application, and the power consumption is less than 350 nW. The measured accuracy of abnormal ECG detection is 90.5%. Moreover, the latency is only$40 \mu \text{s}$to realize real-time NN inference. This work provides an effective solution for AIoT nodes that require both ultralow power and fast response.

The Internet of Things (IoT) is an interface with the physical world that usually operates in random-sparse-event (RSE) scenarios. This article discusses main challenges of IoT chips: power consumption, power supply, artificial intelligence (AI), small-signal acquisition, and evaluation criteria. To overcome these challenges, many works recently aimed at IoT system design have emerged. This work reviews the architecture and circuit innovations that have contributed to IoT developments. This paper does not cover security of IoT. Event-driven architectures and nonuniform sampling ADCs significantly reduce the long-term average power. Besides, embedding AI engines in IoT nodes (AIoT) is one critical trend. The computing-in-memory technique improves the energy efficiency of the AI engine. Asynchronous spike neural networks (ASNNs) AI engines show low power potential. In addition to data processing, small-signal acquisition is also critical. The charge-domain analog-front-end (AFE) techniques such as floating inverter-based amplifiers improve energy efficiency. In addition to the above low power and high energy efficiency technologies, energy harvesting can also enhance the lifetime of AIoT devices. This article discusses recent ambient RF and natural energy harvesting approaches and high-efficiency DC-DC with a wide load range. Finally, novel evaluation criteria are introduced to establish benchmark standards for AIoT chips.