Variations of power and ground levels affect very large scale integration circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise-on-signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply-level-induced jitter characteristics. The expressions can be used in any existing circuit performance optimization design flow or can be combined into any delay calculations as a correction factor.

Variation of power and ground levels affect VLSI circuit performance. Trends in device technology and in packaging have necessitated a revision in conventional delay models. In particular, simple scalable models are needed to predict delays in the presence of uncorrelated power and ground noise. In this paper, we analyze the effect of such noise on signal propagation through a buffer and present simple, closed-form formulas to estimate the corresponding change of delay. The model captures both positive (slowdown) and negative (speedup) delay changes. It is consistent with short-channel MOSFET behavior, including carrier velocity saturation effects. An application shows that repeater chains using buffers instead of inherently faster inverters tend to have superior supply level-induced jitter characteristics.

In this paper we present efficient closed-form formulas to estimate capacitive coupling-induced crosstalk noise for distributed RC coupling trees. The efficiency of our approach stems from the fact that only the five basic operations are used in the expressions: addition (x+y), subtraction (x-y), multiplication (x/spl times/y), division (x/y) and square root (/spl radic/x). The formulas do not require exponent computation or numerical iterations. We have developed closed-form expressions for the peak crosstalk noise amplitude, the peak noise occurring time and the width of the noise waveform. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of performance optimization algorithms or as cost functions to guide routers. They capture the influence of coupling direction (near-end and far-end coupling) and coupling location (near-driver and near-receiver).

This paper presents a new formulation and an efficient solution of the power and ground mesh sizing problem. We use the key observations that (1) the drops in power and ground node potentials are due not only to currents drawn by the computing blocks, but also to those drawn by the clock buffers, and (2) changes of circuit component delays are linearly proportional to the power/ground IR-drops. This leads to a linear quantification of the timing relations between the clocking and computing components in terms of the power/ground IR-drops. Our method removes all IR-drop related timing violations that occur in about 2% of paths when grids are sized using the existing methods that satisfy the maximum IR-drop constraints. In addition, we achieve supply mesh area improvements of the order of 30% while simultaneously reducing the power dissipated in the circuits by about 6.6% compared to traditional grid sizing methods.

In this paper we present efficient closed-form formulas to estimate the incremental delay change induced by capacitive interconnect coupling. We also analyze temporal correlations among switching signals and develop criteria for timing window alignment. Our approximations are conservative and yet achieve acceptable accuracy. The formulas are simple enough to be used in the inner loops of static timing analysis. Categories & Subject Descriptors: J.6 [Computer-Aided Engineering]: Computer-aided design

In this paper, we study signal alignment resulting in maximum peak interconnect coupling noise. We consider three cases. In the first one, we assume that arbitrary arrival times of input signals are feasible. In the second case, we assume that timing windows are given for each aggressor input. The victim is quiet for the above two cases. In the third case, the victim net has a propagated noise from the previous stage and timing windows are given for both the propagating noise and the aggressor inputs. We propose a simple procedure to find aggressor alignment for worst-case coupling in all the cases.

In this paper we study signal alignment resulting in maximum peak interconnect crosstalk noise. We consider two cases. In the first one we assume that arbitrary arrival times of input signals are feasible. In the second case we assume that timing windows are given for each aggressor input. We propose a simple procedure to find aggressor alignment for worst-case coupling in both cases. Keywords Crosstalk noise, aggressor alignment, interconnect coupling, signal integrity, timing window. 1. INTRODUCTION With technology shrinking to deep submicron regime coupling noise becomes a common effect. It is therefore essential to develop techniques that allow estimating accurately worst-case crosstalk conditions. In this paper we study the problem of how crosstalk noise is affected by the switching times of aggressors acting on a victim net. We assume that driver strengths, wire spacing, spatial positions of aggressors and victim are given and not changing. Signal arrival times can be adjust...

We address the problem of crosstalk computation and reduction using circuit and layout techniques in this paper. We provide easily computable expressions for crosstalk amplitude and pulse width in resistive, capacitively coupled lines. The expressions hold for nets with arbitrary number of pins and of arbitrary topology under any specified input excitation. Experimental results show that the average error is about 10% and the maximum error is less than 20%. The expressions are used to motivate circuit techniques, such as transistor sizing, and layout techniques, such as wire ordering and wire width optimization to reduce crosstalk.