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Wei-Chun Kao

dblp:91/2162 · DBLP profile ↗
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6ranked-venue papers
2as first author
0since 2021 · last 2013
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 2 · 1 first-authorSystems, architecture and hardware · 2Graphics, computer vision, multimedia, augmented reality and games · 1Applied, interdisciplinary, general and emerging computing · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Electronic design automation · 62% Interconnection networks and networks-on-chip · 28% Parallel and multicore computing · 10%
Interdisciplinary, comprehensive, and emerging computing
1 paper
Bioinformatics and computational biology · 100%

Topics — the 8 heaviest of 8, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation › physical design › routing
global routing
0.322013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Multi-threaded collision-aware global routing with bounded-length maze routing · DAC 2010
Electronic design automation
physical design
0.322013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Multi-threaded collision-aware global routing with bounded-length maze routing · DAC 2010
Electronic design automation › physical design › routing › wire routing
maze routing
0.212013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Interconnection networks and networks-on-chip › routing algorithms
parallel routing
0.212013
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Interconnection networks and networks-on-chip › interconnection networks
multi-threaded routing
0.222013
Multi-threaded collision-aware global routing with bounded-length maze routing · DAC 2010
NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2013
Bioinformatics and computational biology › sequence analysis
base calling
0.112010
naiveBayesCall: An Efficient Model-Based Base-Calling Algorithm for High-Throughput Sequencing · RECOMB 2010
Bioinformatics and computational biology › genomics
high-throughput sequencing
0.112010
naiveBayesCall: An Efficient Model-Based Base-Calling Algorithm for High-Throughput Sequencing · RECOMB 2010
Parallel and multicore computing
parallel algorithms
0.112010
Multi-threaded collision-aware global routing with bounded-length maze routing · DAC 2010

Methods — techniques the papers use, named apart from their topics

bounded-length maze routing · 0.3rectilinear steiner minimum tree · 0.2task-based concurrency · 0.1naive bayes · 0.1
YearPublicationVenuePosition
2013 NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing
abstract
Modern global routers employ various routing methods to improve routing speed and quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) that perform much faster routing than traditional maze routing algorithms. In addition, a rectilinear Steiner minimum tree aware routing scheme is proposed to guide heuristic-BLMR and monotonic routing to build a routing tree with shorter wirelength. This paper also proposes a parallel multithreaded collision-aware global router based on a previous sequential global router (SGR). Unlike the partitioning-based strategy, the proposed parallel router uses a task-based concurrency strategy. Finally, a 3-D wirelength optimization technique is proposed to further refine the 3-D routing results. Experimental results reveal that the proposed SGR uses less wirelength and runs faster than most of other state-of-the-art global routers with a different set of parameters , , , . Compared to the proposed SGR, the proposed parallel router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route cases, respectively, when running on a 4-core system.
Wen-Hao Liu 0001, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.2
2010 Multi-threaded collision-aware global routing with bounded-length maze routing
abstract
Modern global routers use various routing methods to improve routing speed and the quality. Maze routing is the most time-consuming process for existing global routing algorithms. This paper presents two bounded-length maze routing (BLMR) algorithms (optimal-BLMR and heuristic-BLMR) to perform much faster routing than traditional maze routing algorithms. The proposed sequential global router, which adopts a heuristic-BLMR, identifies less-wirelength routing results with less runtime than state-of-the-art global routers. This study also proposes a parallel multi-threaded collision-aware global router based on a previous sequential global router. Unlike the conventional partition-based concurrency strategy, the proposed algorithm uses a task-based concurrency strategy. Experimental results reveal that the proposed sequential global router uses less wirelength and runs about 1.9X to 18.67X faster than other state-of-the-art global routers. Compared to the proposed sequential global router, the proposed parallel global router yields almost the same routing quality with average 2.71 and 3.12-fold speedup on overflow-free and hard-to-route benchmarks, respectively, when running on an Intel quad-core system.
Wen-Hao Liu 0001, Wei-Chun Kao, Yih-Lang Li, Kai-Yuan Chao
DAC2
2010 naiveBayesCall: An Efficient Model-Based Base-Calling Algorithm for High-Throughput Sequencing
Wei-Chun Kao, Yun S. Song
RECOMB1
2004 Decomposition Methods for Linear Support Vector Machines
abstract
In this letter, we show that decomposition methods with alpha seeding are extremely useful for solving a sequence of linear support vector machines (SVMs) with more data than attributes. This strategy is motivated by Keerthi and Lin (2003), who proved that for an SVM with data not linearly separable, after C is large enough, the dual solutions have the same free and bounded components. We explain why a direct use of decomposition methods for linear SVMs is sometimes very slow and then analyze why alpha seeding is much more effective for linear than nonlinear SVMs. We also conduct comparisons with other methods that are efficient for linear SVMs and demonstrate the effectiveness of alpha seeding techniques in model selection.
Wei-Chun Kao, Kai-Min Chung, Chia-Liang Sun, Chih-Jen Lin
Neural Comput.1
2003 Decomposition methods for linear support vector machines
abstract
We explain that decomposition methods, in particular, SMO-type algorithms, are not suitable for linear SVMs with more data than attributes. To remedy this difficulty, we consider a recent result by S.S. Keerthi and C.-J. Lin (see http://www.csie.ntu.edu.tw//spl sim/cjlin/papers/limit.ps.gz, 2002) that for an SVM which is not linearly separable, after C is large enough, the dual solutions are at similar faces. Motivated by this property, we show that alpha seeding is extremely useful for solving a sequence of linear SVMs. It largely reduces the number of decomposition iterations to the point that solving many linear SVMs requires less time than the original decomposition method for one single SVM. We also conduct comparisons with other methods which are efficient for linear SVMs, and demonstrate the effectiveness of the proposed approach for helping the model selection.
Kai-Min Chung, Wei-Chun Kao, Tony Sun, Chih-Jen Lin
ICASSP (4)2
2003 Radius Margin Bounds for Support Vector Machines with the RBF Kernel
abstract
An important approach for efficient support vector machine (SVM) model selection is to use differentiable bounds of the leave-one-out (loo) error. Past efforts focused on finding tight bounds of loo (e.g., radius margin bounds, span bounds). However, their practical viability is still not very satisfactory. Duan, Keerthi, and Poo (2003) showed that radius margin bound gives good prediction for L2-SVM, one of the cases we look at. In this letter, through analyses about why this bound performs well for L2-SVM, we show that finding a bound whose minima are in a region with small loo values may be more important than its tightness. Based on this principle, we propose modified radius margin bounds for L1-SVM (the other case) where the original bound is applicable only to the hard-margin case. Our modification for L1-SVM achieves comparable performance to L2-SVM. To study whether L1- or L2-SVM should be used, we analyze other properties, such as their differentiability, number of support vectors, and number of free support vectors. In this aspect, L1-SVM possesses the advantage of having fewer support vectors. Their implementations are also different, so we discuss related issues in detail.
Kai-Min Chung, Wei-Chun Kao, Chia-Liang Sun, Li-Lun Wang, Chih-Jen Lin
Neural Comput.2