This paper proposes two novel and compact low-power tunable AC amplifiers with ultra-low high-pass corner frequency. The circuits are based on alternative AC capacitively coupled feedback topologies using novel implementations leading to better performance in terms of area, power and noise efficiency. This is accomplished by a combination of actively boosting the resistive value of a pseudo-resistor (allowing more than two decades of tuning) and an optimization of the active devices required. Measurement results from a fabricated prototype using a$0.18~\mu \text{m}$technology are provided to demonstrate the technique. The proposed amplifiers can provide tunable high-pass corner frequencies ranging from 31 mHz to 7 Hz, with power consumption as low as$0.425~\mu \text{W}$, CMRR of 84 dB, 0.1 mm2 area, 39.7 dB gain, and integrated IRN of$2.42~\mu \text{V}_{\mathrm {rms}}$.

A novel approach to design low-power area-efficient rail-to-rail output single-stage class-AB operational transconductance amplifiers (OTAs) with enhanced large- and small-signal performance to drive large capacitive loads is presented. It is based on a non-linear nested current mirror at the active load of a splitted differential input pair biased in weak inversion that boosts dynamic currents beyond their quiescent value directly at the output branch. As a result, slew rate, DC gain, gain-bandwidth product, settling time and noise performance are improved without additional circuit elements or power consumption. An OTA prototype has been fabricated in a 180-nm CMOS process, consuming a quiescent power of$2.9~\mu \text{W}$from a supply voltage of ±0.5 V and a silicon area of 0.001 mm2. Measurement results validate the advantages of the proposal, exhibiting positive and negative slew rates of 110 V/ms and −58 V/ms, respectively, and a gain-bandwidth product of 136 kHz with a phase margin of 90° for a capacitive load of 160 pF.

A new approach to design super class AB operational transconductance amplifiers (OTAs) with enhanced large-signal and small-signal performance is presented. It is based on employing two nested positive and negative feedback loops at the active load of an adaptively biased differential pair in weak inversion region. As a result, DC gain, gain-bandwidth product, settling time and noise are improved compared to conventional super class AB OTAs without extra circuit nodes or power consumption. Measurement results of a 180 nm CMOS test chip prototype show a current boosting factor higher than 5000 and a nearly ideal current efficiency. Due to the ultra-low quiescent currents and high driving capability, the circuit exhibits an excellent large-signal figure-of-merit (FOML) of 236 V-1. To illustrate the applicability of the proposed approach, a differential sample-and-hold (S/H) circuit was designed and fabricated on the same test chip. Measurement results of the S/H validate the advantages of the proposal.

A micropower regulated cascode CMOS current mirror is presented, combining floating gate and quasi floating gate MOS transistors to achieve both wide swing and class AB operation, respectively. Measurement results for a 0.5 μm CMOS test chip prototype are included, showing that the current mirror can provide a THD at 100 kHz of -44 dB for a supply voltage of ±0.75 V and input current amplitudes 20 times larger than the bias current.

A novel current-mode CMOS RMS-to-DC converter using translinear techniques is introduced. It is based on a Squarer/Divider cell that is implemented using an electronically simulated loop with a novel biasing scheme that allows its operation in two quadrants. The cell is designed using a differential input current and a small signal first order filter to implement the voltage averaging, leading to a compact solution that can be used with low voltage supplies. The converter has been fabricated in a standard 130 nm CMOS process, and measurement results are provided to demonstrate the feasibility of the system.

In this manuscript a novel current-mode technique to implement generic Piecewise-Linear (PWL) functions is presented. The main characteristic of the proposed circuits is that errors are not accumulated by adding linear segments; instead they are local, providing more robust designs. The proposed circuits are designed in a standard 0.18μm CMOS process with 1.8V power supply. Their operation is based on high precision current mirrors, Winner-Take-All (WTA) and Loser-Take-All (LTA) architectures. Robustness was verified by Monte Carlo analysis and temperature variations from —40°C to 80°C.

A 4thorder Butterworth Gm-C filter based on a low-power design technique employing Floating-Gate MOS (FGMOS) transistors is presented. It consists in a topological rearrangement of conventional fully-differential Gm-C structures decreasing the number of active blocks of the filter and relaxing the transconductor requirements at transistor level. Moreover, high linearity is obtained at low and medium frequencies of the pass band. Measurement results from a test chip prototype in a 0.5 μm standard CMOS n-well process are provided and compared with other published circuits, corroborating the advantages of the proposed topology. A static power consumption of 0.76 mW for a 3.3 V supply voltage has been obtained, with a BW tunable from 300 kHz to 850 kHz.

A new family of two stage op-amps with broadband open loop response is introduced. These have a significant reduction of the DC open loop gain and maintain a high gain at frequencies as low as 1 Hz. This provides them with low DC offset. The proposed circuits are based on the Quasi-Floating Gate (QFG) technique, using a novel implementation for active loads that provides a very low effective resistance at DC and very-low frequencies without penalizing the high resistance at the pass band gain significantly. Moreover, a wide-band AC coupling structure also based on QFG transistors has been combined with the proposed technique, rejecting both the differential input DC voltage and the offset introduced by the circuit. These features make the proposed op-amps suitable for biological signal processing, where small amplitude signals are commonly affected by large DC offsets. Cadence simulation results employing a 0.5 micrometers technology are provided for validating the proposed circuits.

A compact analog multiplier/divider circuit operating in current-mode is presented featuring low supply voltage, low area requirements and wide dynamic range. It is suited to standard digital CMOS processes and can be successfully employed in a wide range of analog signal processing applications. Measurement results for a 0.5μm CMOS test chip prototype are presented. The circuit consumes 120μW using a single supply voltage of 1.5V and requires a silicon area of 150μm × 140μm.

A Variable Gain Amplifier (VGA) based on the Gilbert Cell is presented in this paper. A Piecewise-Linear (PWL) circuit is employed to obtain a gain variation linear in dB. The PWL block is based on multiple cascaded simple current mirrors. The VGA was designed in a 0.35nm CMOS process with 3 V supply. The circuit presents 1.7V output swing, 33 dB gain variation (from 2.7 to 35.6 dB) and a bandwidth of 800 KHz.

In this paper, a novel low-voltage low-power implementation of an exponential voltage-to-voltage converter (EVVC) is presented. It is based on a pseudo-exponential approximation whose terms are easily achieved by the nonlinear currents of a class-AB transconductor. The circuit is able to operate correctly for supply voltages as low as VGS+ 2VDSsat. Simulation results in a 0.5mum CMOS technology show a 47 dB output voltage range with linearity error less than plusmn0.5dB at plusmn1.5 V supply voltage. The power dissipation is less than 100muW

A 1.5-V square-root domain (SRD) first-order filter possessing multiple operating points is presented. The basic building blocks of the filter are based on MOS translinear loops and dynamic level shifter techniques, allowing low voltage operation and an extended dynamic range. However the dynamic level shifters introduce positive feedback inducing three operating points to the filter through a negative differential resistance. A detailed analysis of such performance employing a bi-port analysis is offered. Simulation and measurement results are provided in order to demonstrate the analysis and circuits proposed.