An ensemble data-learning approach based on proper orthogonal decomposition (POD) and Galerkin projection (EnPOD-GP) is proposed for thermal simulations of multi-core CPUs to improve training efficiency and the model accuracy for a previously developed global POD-GP method (GPOD-GP). GPOD-GP generates one set of basis functions (or POD modes) to account for thermal behavior in response to variations in dynamic power maps (PMs) in the entire chip, which is computationally intensive to cover possible variations of all power sources. EnPOD-GP however acquires multiple sets of POD modes to significantly improve training efficiency and effectiveness, and its simulation accuracy is independent of any dynamic PM. Compared to finite element simulation , both GPOD-GP and EnPOD-GP offer a computational speedup over 3 orders of magnitude. For a processor with a small number of cores, GPOD-GP provides a more efficient approach. When high accuracy is desired and/or a processor with more cores is involved, EnPOD-GP is more preferable in terms of training effort and simulation accuracy and efficiency. Additionally, the error resulting from EnPOD-GP can be precisely predicted for any random spatiotemporal power excitation.

A thermal simulation methodology derived from the proper orthogonal decomposition (POD) and the Galerkin projection (GP), hereafter referred to as PODTherm-GP, is evaluated in terms of its efficiency and accuracy in a multi-core CPU. The GP projects the heat transfer equation onto a mathematical space whose basis functions are generated from thermal data enabled by the POD learning algorithm. The thermal solution data are collected from FEniCS using the finite element method (FEM) accounting for appropriate parametric variations. The GP incorporates physical principles of heat transfer in the methodology to reach high accuracy and efficiency. The dynamic power map for the CPU in FEM thermal simulation is generated from gem5 and McPACT, together with the SPLASH-2 benchmarks as the simulation workload. It is shown that PODTherm-GP offers an accurate thermal prediction of the CPU with a resolution as fine as the FEM. It is also demonstrated that PODTherm-GP is capable of predicting the dynamic thermal profile of the chip with a good accuracy beyond the training conditions. Additionally, the approach offers a reduction in degrees of freedom by more than 5 orders of magnitude and a speedup of 4 orders, compared to the FEM.

The need for full-chip dynamic thermal simulation for effective runtime thermal management of multicore processors has been growing in recent years due to the rising demand for high-performance computing. In addition to simulation efficiency and accuracy, a high resolution is desirable in order to accurately predict crucial hot spots in the chip. This work investigates a simulation technique derived from proper orthogonal decomposition (POD) for full-chip dynamic thermal simulation of a multicore processor. The POD projects a heat transfer problem onto a mathematical space constituted by a finite set of basis functions (or POD modes) that are generated (ortrained) by thermal solution data collected from direct numerical simulation (DNS). Accuracy and efficiency of the POD simulation technique influenced by the quality of thermal data are examined thoroughly, especially in the areas with high thermal gradients. The results show that if the POD modes are trained by good-quality data, the POD simulation offers an accurate prediction of the dynamic thermal distribution in the multicore processor with an extremely small degree of freedom (DoF). A reduction in computational time over four orders of magnitude, compared to the DNS, can be achieved for full-chip dynamic thermal simulation with a resolution as fine as the DNS. The study has also demonstrated that the POD approach can be used to rigorously verify the accuracy of solutions offered by DNS tools. A practical approach is proposed to further enhance the accuracy and efficiency of the proposed full-chip thermal simulation technique.

A methodology for fast and accurate thermal simulation of integrated circuits (ICs) is presented based on a multiblock reduced order modeling approach. The model projects the heat equation from a physical domain onto a functional space to represent the thermal solution using a small number of degrees of freedom (DOFs). The approach requires no assumptions about the physical geometry, dimensions, boundary conditions or heat flow pathways, as is usually needed for compact or lumped thermal models. The developed multiblock thermal model is applied to FinFET device/circuit structures including a three-block circuit structure consisting of several NAND gates. The model is verified on multiblock structures against a detailed numerical simulation (DNS). It is shown that the developed multiblock model gives accurate thermal solutions for a multiblock IC structure subjected to power pulse excitations whose pulse frequency, width, shape, and shift in time substantially deviate from those used in model construction. In general, the approach offers accurate thermal solutions as detailed as a DNS with a reduction in the numerical DOF by 5 to 6 orders of magnitude.

Process variation continues to increase with new technologies. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a novel technique to reduce variability of metal process variation in SSTA. This novel method maximizes sensitivity cancellation to minimize variability. The developed methodology is simulated with SSTA in 65-nm technology and shows a reduction in variability.

Technology trends show the importance of modeling process variation in static timing analysis. With the advent of statistical static timing analysis (SSTA), multiple independent sources of variation can be modeled. This paper proposes a methodology for modeling metal interconnect process variation in SSTA. The developed methodology is applied in this study to investigate metal variation in SSTA resulting from chemical-mechanical polishing (CMP). Using our statistical methodology, we show that CMP variation has a smaller impact on chip performance as compared to other factors impacting metal process variation.