This paper presents an energy-efficient hybrid circuit designed for full-duplex communication. In a full-duplex type of communication, simultaneous transmission and reception over a shared channel result in the superposition of the inbound and outbound signals. In addition, it also introduces severe self-interference, which distorts the received signal. A hybrid circuit topology using a Strong-Arm Latch (SAL) is proposed for the first time to effectively suppress the echo and separate the received signal from the superimposed signal, while also providing rail-to-rail output swing without using complex equalizer circuits. Therefore, the overall energy efficiency is improved by reducing the complexity of the circuit. Additionally, the SAL hybrid circuit topology employs a tuning circuit in the replica path to eliminate the mismatch between the main driver and the replica driver. A prototype transceiver has been designed and developed using 65 nm CMOS technology, operating at 1.2 V power supply. The measurement results for the full-duplex receiver carried out with a 20 cm FR4 link that has -4.9 dB insertion loss at the Nyquist frequency. The measured received signal of the proposed transceiver has an eye opening of 460 mV, and the power consumption is 3.86 mW with an energy efficiency of 0.32pJ/b and a bit error rate (BER) below$10^{-12}$at a data rate of 12Gb/s.

This article presents a power-efficient echo-cancellation-based hybrid architecture for full-duplex (FD) chip-to-chip interconnects. Conventional FD transceivers employ three separate transconductance stages for signal transmission, replica generation, and signal separation, thereby increasing overall power consumption (PC). The proposed hybrid topology reduces this overhead by integrating a linear resistor within the replica driver (RD) for retrieving the incoming signal from the tri-level superimposed signal at the transceiver interface. This makes the proposed hybrid power-efficient compared to the existing FD hybrid circuit topologies. The prototype design has been fabricated in 1.2-V, 65-nm CMOS technology. The measured results of the proposed hybrid circuit have a received signal with an eye-opening of 20 mV at a data rate of 8 Gb/s over a 20-cm FR4 PCB trace. The proposed hybrid achieves a PC of only 0.3mW and an energy efficiency of 0.075 pJ/bit. The active silicon area occupied by the hybrid is$0.0045~\mathrm {mm}^{2}$.

The transparency property of the N-path mixers made the mixer-first RF front-ends to operate over wide frequency range with tunable impedance matching. However, the requirement of non-overlapping clocks for the RF-sampling N-path mixer causes the power consumption of the clock generation to overwhelm the receiver power consumption. Contrary to RF-sampling mixers, sub-harmonic mixers operating at low clock frequencies save the power consumption of clocking circuitry. However, sub-harmonic mixers are limited to operate at harmonic order of less than N/2 for N-path mixer-first RF front-ends due to their dependency on the number of mixer paths for impedance matching at the RF port. To address this issue, in this work, a novel impedance matching scheme by synthesizing a negative baseband impedance is proposed to facilitate the impedance matching at the desired higher-order harmonic of the sampling frequency. The proposed scheme breaks the tradeoff between the number of paths of the mixer, harmonic order and impedance matching of N-path mixer-first RF front-ends. Also, this work presents a design example using the proposed technique, operating at harmonic order greater than N/2 to validate the proposed idea.

Received signal strength indicator (RSSI) is indispensable in modern wireless communications for detecting and measuring signal strength. This paper presents a new RSSI system architecture that addresses the constraints of conventional designs. Traditional RSSI systems implemented at the RF level encounter challenges such as limited dynamic range and impedance matching, while baseband implementations contend with high power consumption and depend on analog-to-digital converters (ADCs) to digitize signal strength. Moreover, the large dynamic range necessitates high-resolution ADCs, which further exacerbates area and power consumption. The proposed RSSI architecture at baseband mitigates these challenges by employing a limiting amplifier, followed by a peak detector and comparator at each stage, thus eliminating the need for an ADC. This configuration enables coarse control and provides the most significant bits (MSBs) of the RSSI. Additionally, a programmable gain amplifier in conjunction with an up-counter captures the least significant bits (LSBs) of the RSSI, providing fine control. The system is implemented in a 65 nm CMOS process, operating at 1.2 V, with a power consumption of 256 μW. It achieves a wide dynamic range of 80-dB and a detection accuracy of ±0.6 dB, as validated through detailed simulations.

Biologically inspired silicon neuron circuits must accurately mimic real neurons while being compact and low-power. Among all silicon neuron models, integrate-and-fire (I&F) models closely replicate the behaviour of real neurons while maintaining simplicity and computational efficiency. However, existing CMOS-based implementations of I&F neuron models lack optimal circuit performance and energy efficiency, primarily due to leakage and short-circuit currents associated with these designs. This paper presents an energy-efficient I&F silicon neuron (SiN) circuit that can produce biologically plausible neural dynamics by utilising the PMOS bulk cross-coupled inverter pair (PBXCIP) along with a low supply voltage to reduce leakage currents effectively. Moreover, it provides firing threshold tunability with improved control. The proposed SiN is implemented using 65 nm CMOS technology, operating at a supply voltage of 0.2 V, and consumes 350 fJ/spike at a spiking frequency of 30 Hz.

This paper presents an energy-efficient, half-rate charge-steering logic (HR-CSL) based echo cancellation hybrid (ECH) circuit topology for full-duplex(FD) signaling across chip-to-chip interconnects. The proposed charge-steering logic (CSL) based hybrid has much lower power consumption compared to conventional current-mode logic (CML) and voltage-mode logic (VML) based hybrid implementations, thanks to the discrete nature of CSL hybrid topology avoiding direct current path between$V_{DD}$and ground. The prototype test chip design of the proposed hybrid circuit topology has been fabricated in 65 nm CMOS for a 20 cm FR4 PCB chip-to-chip interconnect with a supply voltage of 1.2 V. The measurement performance of the HR-CSL based hybrid circuit achieves 8 Gb/s FD operation at a power consumption of only 0.15 mW with an energy efficiency of 0.0375 pJ/bit. The measurement results show that the proposed hybrid circuit has a differential received signal voltage swing of 110 mV at 8 Gb/s data rate with a timing jitter of 20 ps. The proposed hybrid has a clock phase margin of 25% UI at bit-error-rate (BER) less than$10^{-12}$. The active area of the hybrid is 0.0007 mm2.

The conventional power-hungry current and voltage-mode hybrid circuit topologies are not suitable for full-duplex(FD) front-end receivers, and they are not directly compatible with modern digital signal processing (DSP) cores as they suffer from low output differential eye-opening at high data rates. Moreover, they require extensive equalization and post-amplifier circuits to improve the eye-opening of the received signal at the cost of an additional power penalty and the increased circuit complexity. As a result, the overall energy-efficiency of the transceiver circuit becomes poor. To address this issue, in this work, the authors propose a half-rate StrongArm latch comparator based hybrid(HR-SALCH) for FD signaling over off-chip interconnect. The StrongArm latch comparator(SALC) circuit topology has the advantages of rail-to-rail voltage swing, digital equalization, and low static power dissipation and hence it is suitable candidate for realizing an energy-efficient receiver front-end hybrid circuit in FD off-chip communication. The proposed StrongArm latch comparator based hybrid(SALCH) is designed in 1.2 V, 65 nm CMOS at 6-Gb/s FD data rate over FR4-PCB interconnect of length 20 cm. The post-layout simulation results show that the proposed full-duplex transceiver deploying SALCH circuit topology has rail-to-rail output voltage swing with the timing jitter of 11 ps. The power consumption of the SALCH circuit topology is only 0.62 mW with an energy efficiency of 0.2 pJ/b at 6-Gb/s full-duplex operation.

The conventional current-mode pseudo-random bit sequence (PRBS) generators suffer from high-power consumption, low output voltage swing and they are not directly compatible with the CMOS static logic circuit. To address this issue, this work proposes power-efficient, 27-1, 20-Gb/s, half-rate pseudo-random bit sequence(HR-PRBS) generators by employing current-integrating latch circuit topology using incomplete settling at 20-Gb/s data rate implemented in 1.2 V, 65 nm CMOS. The proposed current-integrating logic latch based PRBS implementations achieves low power consumption, high speed and high voltage swing thanks to incomplete settling behaviour of the CIL circuit topology. The proposed PRBS generator implementations employing current-integrating latch topology consumes power of 0.76-mW/Gb/s while operating at 20-Gb/s data rate. The differential eye-opening of the proposed current-integrating logic (CIL) HR-PRBS generator is 1.6 V at 20-Gb/s date rate.

This work proposes a 27-1, low power, half-rate, StrongArm latch based pseudo-random bit sequence (SAL-PRBS) generator at a 15-Gb/s data rate. The proposed SAL-PRBS consumes low static-power consumption compared to current-mode logic (CML) based PRBS circuit topologies, thanks to the StrongArm latch (SAL) comparator circuit topology having virtually zero static power consumption. The proposed design is implemented in 1.2 V, 65 nm CMOS. The simulation results show that the SAL-PRBS consumes only 3.7 mW at a 15-Gb/s data rate. The output data sequence of SAL-PRBS has rail-to-rail output voltage signal swing with a timing jitter of 2 ps. The figure-of-merit(FoM) of the proposed SAL-PRBS generator is only 0.036-pJ/bit at a 15-Gb/s data rate.

Subsampling down-conversion has not been a popular choice for mixer-first RF front-ends for two interdependent reasons. One, the subsampling down-conversion is inherently heterodyne in nature. Two, as a consequence to one, the passive mixer transparency property can not be exploited for providing impedance matching at the RF port by impedance translation. In this work, an eight-path quarter-rate subsampling (QRSS) mixer-first direct down-conversion architecture is proposed to address these issues. The proposed architecture simultaneously achieves quadrature direct down-conversion and impedance matching by using the third harmonic of the QRSS frequency,$f_s$. The impedance matching is achieved by exploiting the eight-path passive mixer transparency property. Compared to RF sampling receivers, this architecture employs a sampling frequency$f_s$three times lesser than$f_{\text{RF}}$, saving on the power consumption of nonoverlapping clock generation, distribution circuits, and frequency synthesizer. A test chip is fabricated in 1.2-V, 65-nm CMOS with an active area of 0.32 mm$^2$. The subsampling eight-path mixer, baseband low-noise amplifier (LNA), and g$_m$-cell consume a power of 800$\mu$W, 23 mW, and 3 mW, respectively, for a target bandwidth of 90 MHz. Nonoverlapping clock generation circuit consumes 2–9.2 mW, over the band 0.4–1.8 GHz. The receiver has a double sideband (DSB) noise figure of 4.7 dB, a conversion gain of 22 dB, an in-band (IB)-IIP$_3$of$-$1 dBm, and OB-IIP$_3$of$+$8 dBm.

Reconfigurable subsampling mixer-first RF front-end is a potential candidate for low-power applications as it operates at a low clock frequency and hence consumes low power. However, the subsampling down-conversion has not been employed in mixer-first RF front-ends due to the disadvantage of high noise figure from inherent noise folding and lack of RF port impedance matching because of nonzero IF down-conversion. To address the above two issues, first, a subsampling multipath down-conversion mixer scheme is proposed for rejecting$3f_{s}/4$and$5f_{s}/4$down-conversions, thereby alleviating the effect of noise folding, leading to low noise figure. Second, an IF-stage impedance matching scheme is proposed that provides$50~\Omega $matching at the RF port of the mixer using an IF-LNA in shunt with an$M$-phase switch-capacitor filter. The analysis of the proposed scheme in terms of noise figure, conversion gain, and harmonic rejection is presented. The proposed subsampling mixer-first RF front-end is implemented in 1.2 V, 65-nm CMOS technology. The prototype occupies an active area of 0.33 mm2, the switch-capacitor mixer and$M$-phase filter consume$400~\mu \text{W}$of power, and IF amplifier and nonoverlapping clock generation circuit consume 25 mW and 6–12.6 mW of power, respectively. The RF front-end achieves a 6.5-dB noise figure, 15.1-dB conversion gain, 50-dB harmonic rejection ratio (HRR), and +10-dBm IB-IIP3.

In this paper, an energy efficient current-mode hybrid circuit topology for echo-cancellation is proposed for full-duplex signalling over chip-to-chip interconnects. Conventional full-duplex transceivers consists of three transcondutors, namely, for transmitting the outbound signal, for replica generation and for cancellation or subtraction, leading to an increase in the power consumption. However, the proposed hybrid circuit topology consists of only two transconductors, transmitter and replica generator. The separation of the inbound signal from the signal on the line is achieved using a simple resistor, thereby eliminating the need of additional transconductor for subtraction. This makes the proposed hybrid an attractive choice for realizing power efficient full-duplex transceiver compared to the existing transceiver with current-mode and voltage-mode hybrid circuit topologies. The proposed hybrid is implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout simulation including the package parasitic has a differential received signal voltage swing of 85 mV at 10 Gb/s data rate over a 20-cm FR4 PCB trace. The total power consumption of the hybrid is 0.29 mW and the corresponding energy efficiency is 0.057 pJ/bit. The layout of the hybrid occupies an area of 0.00025 mm2.

In this paper, a low-power half-rate charge-steering echo cancellation hybrid circuit topology is proposed for full-duplex signaling over chip-to-chip interconnects. The proposed half-rate charge-steering hybrid topology has a very low power consumption compared to traditional current-mode and voltage-mode hybrid circuit topology implementations, thanks to the discrete nature of charge-steering hybrid topology avoiding direct current path between VDDand ground. The half-rate hybrid circuit topology has been implemented in 65 nm CMOS technology with a supply voltage of 1.2 V. The post-layout performance of the half-rate charge-steering hybrid including package parasitic has a differential received signal voltage swing of 0.8 V at 10 Gb/s data rate with a timing jitter of 10 ps over a FR4 PCB interconnect of length 20 cm. The total power consumption of the half-rate charge-steering hybrid is only 0.16 mW and its energy efficiency is 0.032 pJ/bit. The layout of the hybrid occupies an area of 0.0007 mm2.

Sub-sampling down-conversion mixers have not been considered as a mixer-first RF front-ends due to their disadvantages of high noise figure and lack of impedance matching at the RF port, even though they offer the advantages of less complex clocking circuits and low-power consumption. In this work, a process scalable architecture for low noise figure impedance matched sub-sampling mixer-first RF front-end is proposed addressing the issues of noise folding and impedance matching with process scalable circuit components like switches, capacitors and inverters. A scheme to reject the selected IF odd-harmonics of fs/4 by multi-path sampling is proposed, alleviating the effect of noise folding and leading to low noise figure sub-sampling mixer-first RF front-end. The combination of the complex impedance band-pass filter along with the IF-LNA provide the tuned impedance matching. In addition, analysis on sub-sampling frequency plan, amount of harmonic rejection and its effect on noise figure, transparency of the impedance at the RF port and its tunability with respect to the input impedance of IF-LNA is presented. To validate the analysis and modeling, as well as to explain the architecture, an example low-power narrow-band IoT(NB-IoT) standard RF front-end is realized in 1.2 V, 65 nm CMOS and it is observed that the performance predicted by analytical equations is in agreement with Spectre RF simulations.

Full-duplex communication over on-chip interconnects requires a hybrid circuit that separates the inbound signal from the superimposed signal by subtracting the outbound signal. This operation results in an echo and incomplete cancellation of this echo leads to residue. Non-zero residue reduces the amplitude and timing margins in the recovered signal eye-diagram. This work for the very first time proposes an adaptive transceiver for near zero-residue for full-duplex communication over on-chip interconnects by deploying a residue monitor. The proposed hybrid circuit topology employs low power charge-mode integrated circuits compared to traditional high power consuming current-mode and voltage-mode echo-cancellation circuits. In the proposed scheme, the operation of cancelling the outbound signal is assisted by a replica generation stage which replicates the outbound signal in terms of signal swing is realized by the digitally re-configurable capacitor-bank. The echo-cancellation is implemented at the circuit level in 1.2V, 65 nm CMOS over a 1-mm on-chip interconnect and the residue monitor architecture is realized with behavioural modeling in Verilog-AMS. The proposed scheme operates at a data rate of 10-Gb/s with a total power consumption of 9.64 mW. The loop locks for a control voltage of 173 mV with an adaptation time of 5.74 ns and the corresponding swing of the replica signal is 230.13 mV with a final residue of only 3.13 mV. The extracted inbound signal has a differential swing of 154 mV.

This work presents a new hybrid circuit topology for simultaneous bidirectional signaling over on-chip interconnects in a multi-channel signaling environment. The proposed hybrid circuit topology transmits the outbound signal and simultaneously receives the inbound signal from the combined sign al, which is a superposition of the outbound and inbound signals, thanks to the echo cancellation circuitry integrated into the hybrid topology. The echo cancellation circuitry cancels the outbound signal, called the replica signal from the super-imposed signal on the channel. The replica signal is generated in the hybrid circuit without the need for a separate replica circuit stage. This work is implemented in 1.1 V, 65-nm CMOS technology. The performance results shows that the proposed hybrid circuit operates at a data rate of 16-Gb/s/ch over a 3 mm on-chip interconnect of width 2 μm in a eight parallel channel environment and it achieves an transmitted signal swing of 520 mV and a received signal swing of 100 mV for a power consumption of 24.6 mW.

The limited power budget of a multiple sensor system such as a wireless body area network (WBAN) necessiates both power efficient sensing architecture and low power circuit implementation. A sparse recovery based sub-Nyquist signal acquisition technique called compressed sensing has been proposed recently, which enables lower power and lesser complexity in the sensing front end. In this work, a low power multichannel EEG signal acquisition system based on distributed compressed sensing has been proposed which performs simultaneous sensing and recovery of multiple sparse signals with compression ratios greater than an individual channel compression. Charge mode switched capacitor circuit techniques are employed to perform the core compressed sensing measurements to reduce power consumption. The system is implemented in a 1.8 V, 0.18 μm CMOS technology with a discrete time sampling based charge domain analog front-end. A single multiplexed 8-bit SAR ADC has been designed and integrated to digitize the measurements from all channels. The system has been tested with a set of EEG signals from practical neural recordings and the results show an average PSNR of 22.17 dB while sensing 64-channels simultaneously at a compression ratio (CR) of up to 1/4.

This work proposes an integrated remote terminal and bus controller: MIL-STD-1553+, implemented in 1.2 V 65-nm CMOS technology occupying 115470 μm2of area. It incorporates a synchronous back-end and host processor interface to a true dual port memory for faster memory accesses. Employing a majority-based sampling free-running decoder at its front-end and scaled-up protocol state machines in its control unit, this redesigned controller achieves 100-Mb/s with BER of 10−7over 1553 buses, consuming a total power of 29.86 mW.

High-density wireless intracranial neural recording is a promising technology enabling the autonomous diagnosis and therapy of brain diseases. Increasing the number of recording channels is accompanied by the increased amount of data resulting in an unacceptable transmission power. A comprehensive study of possible compressed sensing methods in the context of neural signals has been done, and the compression of signals originating from different channels in the spatial domain has been implemented at the system and circuit levels. Results of the simulations in a UMC 0.18μm CMOS technology and subsequent reconstructions show the possibility of compressing with ratios as high as 2.6 with a recovery SNR of at least 10dB using extremely compact and low-power circuits. The power efficiency and limited area per channel confirm the relevance of the proposed approach for multi-channel high-density neural interfaces.