An integrated computer-aided design (CAD) framework for evaluating MOSFET and layout parasitic extraction (LPE) models and circuit simulators used in the timing and power analysis of CMOS products is presented. This unified CAD methodology builds a step-wise understanding of the underlying parameter values in the models and their impact on circuit performance. A number of circuit experiments are included to extract the contributions of key MOSFET parameters and physical layout sensitive parasitic elements from circuit simulation results. This CAD setup thus allows easy and detailed comparison of different technologies, device models, and LPE tools to prevent possible bugs in the software as well as inaccuracies in device and parasitic models and timing tools. The software code to carry out the circuit simulations, analysis, and display of the results in an automated fashion has been specifically developed to support this framework. Some of the experiments designed for this work are also placed on the product chip for model-to-hardware correlation. The comparison of the hardware data to the model predictions points to the sources of any discrepancies and aids in tuning the product design to reflect changes in the technology as part of an overall design for manufacturing (DFM) platform

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first-order delay model that takes into account both correlated and independent randomness is proposed. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivity of all timing quantities to each of the sources of variation is available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature, which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in computer time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial application-specified integrated circuit (ASIC) chips with over two million logic gates, and statistical timing results are compared to exhaustive corner analysis on a chip design whose hardware showed early mode timing violations

Variability in digital integrated circuits makes timing verification an extremely challenging task. In this paper, a canonical first order delay model is proposed that takes into account both correlated and independent randomness. A novel linear-time block-based statistical timing algorithm is employed to propagate timing quantities like arrival times and required arrival times through the timing graph in this canonical form. At the end of the statistical timing, the sensitivities of all timing quantities to each of the sources of variation are available. Excessive sensitivities can then be targeted by manual or automatic optimization methods to improve the robustness of the design. This paper also reports the first incremental statistical timer in the literature which is suitable for use in the inner loop of physical synthesis or other optimization programs. The third novel contribution of this paper is the computation of local and global criticality probabilities. For a very small cost in CPU time, the probability of each edge or node of the timing graph being critical is computed. Numerical results are presented on industrial ASIC chips with over two million logic gates.

High frequency on-chip interconnect examples are accurately analyzed using full-wave PEEC (Partial Element Equivalent Circuit) analysis. All wire currents and voltages (or delays) are visualized using 3D animations to aid intuitive understanding of new, high frequency interconnect effects.

With the advances in the speed of high-performance chips, inductance effects in some on-chip interconnects have become significant. Specific networks such as clock distributions and other highly optimized circuits are especially impacted by inductance. Several difficult aspects have to be overcome to obtain valid waveforms for problems where inductances contribute significantly. Mainly, the geometries are very complex and the interactions between the capacitive and inductive currents have to be taken into account simultaneously. In this paper, we show that a full-wave partial element equivalent circuit method, which includes the delays among the partial elements, leads to an efficient solver enabling the analysis of large meaningful problems. Applying this method to several examples leads to helpful insights for realistic very large scale integration wiring problems. It is shown in this paper that the impact overshoot, reflections, and inductive coupling are critical for the design of critical on-chip interconnects.

Article Free Access Share on Dealing with inductance in high-speed chip design Authors: Phillip Restle IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Albert Ruehli IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile , Steven G. Walker IBM T.J. Watson Research Center, Yorktown Heights, NY IBM T.J. Watson Research Center, Yorktown Heights, NYView Profile Authors Info & Claims DAC '99: Proceedings of the 36th annual ACM/IEEE Design Automation ConferenceJune 1999 Pages 904–909https://doi.org/10.1145/309847.310096Published:01 June 1999Publication History 23citation453DownloadsMetricsTotal Citations23Total Downloads453Last 12 Months58Last 6 weeks7 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF