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K. V. Anjan

dblp:91/2647 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 1995
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Interconnection networks and networks-on-chip · 76% Electronic design automation · 19% Performance modeling and evaluation · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Interconnection networks and networks-on-chip › routing algorithms
adaptive routing
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995
Interconnection networks and networks-on-chip › deadlock handling
deadlock recovery
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995
Interconnection networks and networks-on-chip
router
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995
Electronic design automation › physical design
routing
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995
Interconnection networks and networks-on-chip
virtual channels
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995
Performance modeling and evaluation
simulation
0.011995
An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA · ISCA 1995

Methods — techniques the papers use, named apart from their topics

simulation · 0.0
YearPublicationVenuePosition
1995 An Efficient, Fully Adaptive Deadlock Recovery Scheme: DISHA
abstract
This paper presents a simple, efficient and cost effective routing strategy that considers deadlock recovery as opposed to prevention. Performance is optimized in the absence of deadlocks by allowing maximum flexibility in routing. Disha supports true fully adaptive routing where all virtual channels at each node are available to packets without regard for deadlocks. Deadlock cycles, upon forming, are efficiently broken by progressively routing one of the blocked packets through a deadlock-free lane. This lane is implemented using a central floating deadlock buffer resource in routers which is accessible to all neighboring routers along the path. Simulations show that the Disha scheme results in superior performance and is extremely simple, ensuring quick recovery from deadlocks and enabling the design of fast routers.
K. V. Anjan, Timothy M. Pinkston
ISCA1