Demo Data from EDBT 2026 / reviewers in the wild / expert
Yung-Te Lai
dblp:91/2850
· DBLP profile ↗
9ranked-venue papers
8as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 9 · 8 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
5 papers |
Electronic design automation · 100% | |
| Theoretical computer science
2 papers |
Algorithms and data structures · 57% Mathematical optimization · 43% |
Topics — the 11 heaviest of 11, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › logic synthesis
boolean function decomposition |
0.0 | 3 | 1996 | OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis · DAC 1993 |
Electronic design automation
logic synthesis |
0.0 | 3 | 1996 | OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis · DAC 1993 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 2 | 1996 | Formal Verification Using Edge-Valued Binary Decision Diagrams · IEEE Trans. Computers 1996 Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification · DAC 1992 |
Electronic design automation › hardware verification and test
formal verification |
0.0 | 1 | 1996 | Formal Verification Using Edge-Valued Binary Decision Diagrams · IEEE Trans. Computers 1996 |
Electronic design automation › logic synthesis › technology mapping
FPGA technology mapping |
0.0 | 1 | 1996 | OBDD-based function decomposition: algorithms and implementation · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1996 |
Algorithms and data structures
decision diagrams |
0.0 | 1 | 1996 | Formal Verification Using Edge-Valued Binary Decision Diagrams · IEEE Trans. Computers 1996 |
Electronic design automation › hardware verification and test › formal verification
equivalence checking |
0.0 | 1 | 1994 | EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › hardware verification and test › functional verification
logic verification |
0.0 | 1 | 1994 | EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Mathematical optimization
integer programming |
0.0 | 1 | 1994 | EVBDD-based algorithms for integer linear programming, spectral transformation, and function decomposition · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 1994 |
Electronic design automation › logic synthesis
FPGA synthesis |
0.0 | 1 | 1993 | BDD Based Decomposition of Logic Functions with Application to FPGA Synthesis · DAC 1993 |
Electronic design automation › hardware verification and test › formal verification
hierarchical verification |
0.0 | 1 | 1992 | Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification · DAC 1992 |
Methods — techniques the papers use, named apart from their topics
edge-valued binary decision diagrams · 0.1structural EVBDDs · 0.0spectral transformation · 0.0ordered binary decision diagrams · 0.0common subfunction identification · 0.0binary decision diagram · 0.0EVBDD · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Formal Verification Using Edge-Valued Binary Decision DiagramsabstractWe present a new data structure called edge-valued binary-decision diagrams (EVBDD). An EVBDD is a directed acyclic graph, that provides a canonical and compact representation of functions that involve both Boolean and integer quantities. In general, EVBDDs provide a more versatile and powerful representation than ordinary binary decision diagrams. We first describe the structure and properties of EVBDDs, and present a general algorithm for performing a variety of binary operations. Next, we describe an important extension of EVBDDs, called Structural EVBDDs, and show how they can be used for hierarchical verification. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
IEEE Trans. Computers | 1 |
| 1996 | OBDD-based function decomposition: algorithms and implementationabstractThis paper presents algorithms for disjunctive and nondisjunctive decomposition of Boolean functions and Boolean methods for identifying common subfunctions from multiple Boolean functions. Ordered binary decision diagrams are used to represent and manipulate Boolean functions so that the proposed methods can be implemented concisely. These techniques are applied to the synthesis of look-up table based field programmable gate arrays and results are presented. Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1994 | FPGA Synthesis Using Function DecompositionabstractPresents two Boolean methods for identifying common subfunctions from multiple-output functions. The first method is based on encoding the distinct columns in the stacked decomposition chart of the multiple-output function; the second method is based on the examination and encoding of all possible subfunctions that can be generated from a function with respect to a given subset of input variables. We then apply these methods to the synthesis of lookup-table based field programmable gate arrays. Experimental results are very encouraging.> Yung-Te Lai, Kuo-Rueih Ricky Pan, Massoud Pedram |
ICCD | 1 |
| 1994 | EVBDD-based algorithms for integer linear programming, spectral transformation, and function decompositionabstractEdge-Valued Binary-Decision Diagrams (EVBDD's) are directed acyclic graphs that can represent and manipulate integer functions as effectively as Ordered Binary-Decision Diagrams OBDD's) do for Boolean functions. They have been used in logic verification for showing the equivalence between Boolean functions and arithmetic functions. In this paper, we present EVBDD-based algorithms for solving integer linear programs, computing spectral coefficients of Boolean functions, and performing function decomposition. These algorithms have been implemented in C under the SIS environment and experimental results are provided.> Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 1 |
| 1993 | BDD Based Decomposition of Logic Functions with Application to FPGA SynthesisabstractThis paper presents a theory for (disjunctive and nondisjunctive) function decomposition using the BDD representation of Boolean functions.Incompletely specified as well as multi-output Boolean functions are addressed as part of the general theory.A novel algorithm (based on an EVBDD representation) for generating the set of all bound variables that make the function decomposable is also presented.We compared our BDD-based decomposition procedure with existing implementations of the Roth-Karp procedure and obtained significant speed-ups.1 Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
DAC | 1 |
| 1993 | FGILP: an integer linear program solver based on function graphsabstractEdge-valued binary-decision diagrams (EVBDDs) are directed acyclic graphs which can represent and manipulate integer functions as effectively as ordered binary-decision diagrams (OBDDs) do for Boolean functions. They have been used to perform logic verification and compute the decomposability of Boolean functions. In this paper, we present a new EVBDD application for solving integer linear programs (ILP), which is an NP-hard problem that appears in many applications. Our approach is to combine the benefits of the EVBDD data structure (in terms of subgraph sharing and caching of computational results) with the state-of-the-art ILP solving techniques. Our program, called FGILP (Function Graph ILP) has been implemented in C under the SIS environment. The preliminary results of FGILP are comparable to those of LINDO. Yung-Te Lai, Massoud Pedram, Sarma B. K. Vrudhula |
ICCAD | 1 |
| 1992 | Edge-Valued Binary Decision Diagrams for Multi-Level Hierarchical Verification
Yung-Te Lai, Sarma Sastry |
DAC | 1 |
| 1992 | Boolean Matching Using Binary Decision Diagrams with Applications to Logic Synthesis and VerificationabstractAn algorithm for Boolean matching based on binary decision diagrams using a level-first search strategy is presented. This algorithm is generally not restricted to circuits with just a few inputs and can be used for both technology mapping and logic verification. Unlike depth-first and breadth-first strategies, a level-first strategy permits significant pruning of the search space. A set of filters that further improve the performance of the matching algorithm is described. A method of analyzing the effectiveness of a filter is presented, and the various filters are ranked on the basis of their effect/cost ratio. Experimental results on a number of benchmark circuits are presented, comparing the basic matching algorithm with and without the use of various filters. It is shown how the matching algorithm and the filters can be extended to Boolean functions with don't cares.> Yung-Te Lai, Sarma Sastry, Massoud Pedram |
ICCD | 1 |
| 1983 | Performance Evaluation of the Largest-first/First-fit Dynamic Storage Allocation Technique
John L. Carroll, Leland L. Beck, Yung-Te Lai |
Performance | 3 |