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Daniel Reaume

dblp:91/2926 · DBLP profile ↗
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2ranked-venue papers
0as first author
0since 2021 · last 1994
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1Theory of computation · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Integrated circuit design · 72% Emerging computing paradigms · 22% Processor architecture and microarchitecture · 6%

Topics — the 6 heaviest of 6, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Emerging computing paradigms
approximate and stochastic computing
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994
Integrated circuit design › digital circuit design
arithmetic circuit design
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994
Integrated circuit design
digital circuit design
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994
Integrated circuit design
residue number system arithmetic
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994
Processor architecture and microarchitecture › pipelining
parallel-pipeline architecture
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994
Integrated circuit design
VLSI design
0.011994
Large Dynamic Range Computations over Small Finite Rings · IEEE Trans. Computers 1994

Methods — techniques the papers use, named apart from their topics

scaling · 0.0quantization analysis · 0.0multivariate mapping · 0.0
YearPublicationVenuePosition
1994 Large Dynamic Range Computations over Small Finite Rings
abstract
Presents a new multivariate mapping strategy for the recently introduced Modulus Replication Residue Number System (MRRNS). This mapping allows computation over a large dynamic range using replications of extremely small rings. The technique maintains the useful features of the MRRNS, namely: ease of input coding; absence of a Chinese Remainder Theorem inverse mapping across the full dynamic range; replication of identical rings; and natural integration of complex data processing. The concepts are illustrated by a specific example of complex inner product processing associated with a radix-4 decimation in time fast Fourier transform algorithm. A complete quantization analysis is performed and an efficient scaling strategy chosen based on the analysis. The example processor uses replications of three rings: modulo-3, -5, and -7; the effective dynamic range is in excess of 32 b. The paper also includes very-large-scale-integration implementation strategies for the processor architecture that consists of arrays of massively parallel linear bit-level pipelines.>
Neil M. Wigley, Graham A. Jullien, Daniel Reaume
IEEE Trans. Computers3
1991 Small moduli replications in the MRRNS
abstract
The authors describe mapping, scaling, and conversion processes using a new mapping strategy for the modulus replication residue number system (MRRNS). The strategy allows direct mapping of bits of either a purely real or multiplexed bit coded complex number to a set of independent rings, defined by moduli 3, 5, and 7. The MRRNS technique is superior to a large QRNS system operating with a computational dynamic range of over 27 b. A classical radix-4 implementation of a 1024 FFT is used for the comparison. The scaling and conversion procedure is shown to be a set of finite ring calculations followed by an array of ordinary binary adders. The VLSI implementation of the most complex finite ring circuit required (a Mod 7 multiplier) is shown to be easily implemented using the switching tree approach, and mask extracted simulations at 50 MHz demonstrate the embedding of the switching trees in a dynamic pipeline/evaluate circuit with restoring latch.>
Neil M. Wigley, Graham A. Jullien, Daniel Reaume, William C. Miller
IEEE Symposium on Computer Arithmetic3