We present a method and tool for examining an FPGA-based circuit, in particular an implementation of a cryptographic algorithm, subjected to a fault injection attack based on clock glitching. The proposed approach offers some unique features that allow us to thoroughly analyse the impact of injected faults on the operation of the circuit. In particular, through precise adjustment of the frequency of an external clock generator, the number of faults occurring at the output of the circuit under test can be observed and controlled. The effectiveness of the proposed approach has been assessed for the AES implementation, leading to a number of practical guidelines that may be essential when planning experimental studies on fault injection in FPGA-based circuits.

A tool for managing finite state machines was developed and presented in this paper. The tool uses an algorithm of serial decomposition to perform operations on these FSMs. With the help of these operations, reduction in size of the combinational part of the circuit can be achieved, leading to smaller memory requirements. The resulting FSM implemented using an FPGA is provided with concurrent error detection (CED). The presented tool offers the designer an opportunity to trade-off error detection efficiency and implementation cost.

We propose a concurrent error detection (CED) scheme for a network of combinational logic blocks implemented with memory embedded in FPGAs. The proposed scheme is proven to detect - without latency - any permanent or transient fault associated with a single input or output of any component of the network. The experimental results show that the overhead for the presented CED technique is low (23.9% for the examined network), especially when compared with solutions intended for gate-based designs (55% or 81%, depending on the technique, for the same network).

We propose a cost-efficient concurrent error detection (CED) scheme for FSMs designed for implementation with embedded memory blocks(EMBs) available in today's SRAM-based FPGAs. The scheme is proven to detect each permanent or transient fault associated with a single input or output of any component of the circuit that results in its incorrect state or output. The experimental results obtained using our proprietary FSM synthesis tool show that despite the heterogeneous structure of the proposed CED scheme, the overhead is very low. For the examined benchmark circuits, the overhead in terms of extra EMBs is in the range of 5.0% to 56.3%, with an average value of 26.5% This compares favorably with the earlier proposed solutions applicable to conventional FSM designs intended for an implementation with gates and flip-flops for which an overhead exceeding 100% is quite typical.

We present several low-cost concurrent error detection schemes for a sequential circuit implemented using FPGAs with embedded memory blocks. The experimental results show that for many of the examined circuits, a reasonable level of error detection can be obtained at the circuitry overhead of less than 10% - a level recommended by proponents of a "pragmatic" approach to on-line testing.

We show that in the case when the set of vector pairs that occur at the input of a combinatorial network in the system environment is restricted (as it is for most applications), the information on such restrictions should be accounted for when evaluating the quality of testing delay faults, especially if the test sequence "mimics" the normal operation, i.e. if only those vector pairs that may occur in normal operation are applied during testing.

Testing delay faults in FPGAs differs significantly from testing delay faults in circuits whose combinational sections can be represented as gate networks. Based on delay fault testability conditions, formulated in a form suitable for analysis of LUT-based FPGAs, we develop an original method for the evaluation of delay fault testability of LUT functions. It relies on an indicator called delay fault activation profile. The proposed method supports an analysis and comparison of different procedures for the enhancement of detectability of FPGA delay faults that rely on transformations of user-defined functions of LUTs in the combinational logic block under test. We demonstrate the effectiveness of our method by applying it to prove the efficiency and to optimize a specific procedure for the transformation of LUT functions which preserves the blocking capability and input-output transition pattern of original functions.

A procedure for the design of robustly path-delay-fault testable two-level circuits by adding extra inputs to the circuits, using the method called Boolean space expansion is proposed. 100% path delay fault testable two-level circuits are achieved with area overhead in the range of 3% to 30%. A procedure to make the multilevel circuits fully testable is also reported. The results for several ISCAS benchmark circuits are presented.>

We show how to design a self-testable RAM using the Circular Self-Test Path technique. The proposed solution, which implements the idea of random testing, offers much higher test quality than deterministic RAM self-test schemes. A 256-Kbit embedded memory can be efficiently tested within 1 second. Such a memory is tested concurrently with other VLSI chip modules.

The effectiveness of a random built-in self-test technique for VLSI circuits is studied. This technique, called the circular self-test path (CSTP), is applicable to circuits that consist of combinational blocks and registers. In particular, the effectiveness of test pattern generation, the effectiveness of test response compaction and fault coverage are examined. The test generation effectiveness is evaluated by the fraction of all possible test patterns applied during a testing session to the circuit under test. The compaction effectiveness of the CSTP technique is measured by the probability of aliasing, and fault coverage by the fraction of all permanent faults that are detected. For all these measures, simple formulas are developed, which give very accurate estimations without detailed circuit simulation. To demonstrate their accuracy, the estimates obtained by the formulas are compared to the results obtained by extensive simulation experiments.>

A method for designing combmationsd circuits suitable for pseudoexhaustive testing is presented.Unlike the conventional approach, where the development of a pseudoexhaustive testing scheme is an afterthought of the functional design, in our method the testabtity criteria are included in the mainstream of the logic synthesis process.The experimental results indicate that a significant reduction of testing time at a negligible area/performance penalty can be obtained its the circuits designed using the proposed procedure.

It is shown that the common belief that any optimized, i.e., nonredundant, circuit is easier to test than its nonoptimized counterpart is not fully justified. It is demonstrated by example that a redundant circuit may be more suitable for random testing than its optimized counterpart. A rule which specifies when redundancy is likely to enhance random testability of a two-level AND-OR gate network is formulated.>

A technique for designing self-test VLSI circuits, referred to as circular self-test path (CSTP), is introduced. The CSTP is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data communication capability. It serves simultaneously for test pattern generation and test response compaction, thereby minimizing the test schedule complexity; the whole chip is tested in a single test session. A distinguishing attribute of built-in self-test (BIST) chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs, but substantially lower than that of built-in logic block observer (BILBO)-based circuits. Theoretical and simulation studies were performed to demonstrate that the test pattern generation efficiency of the CTSP is comparable to that of a pseudorandom generator, regardless of the functionality of the circuit under test.>

A new technique for designing self-testing VLSI circuits, referred to as Circular Self-Test Path, is presented The Circular Self-Test Path is a feedback shift register (output of the last flip-flop is supplied to the first flip-flop) with a data compaction capability. A distinguishing attribute of self-testing chips designed using this technique is a low silicon area overhead, slightly exceeding that of scan path designs. A theoretical analysis and comprehensive simulation experiments we performed to demonstrate that the effectiveness of test pattern generation for the circular self-test path is comparable to that of an ideal pseudorandom test generator.

A method is presented for estimating the maximum operating speed of NMOS self-testing circuits designed using the BILBO technique. The unique feature of this method is that the speed estimation is based only on parameters of the original design (without built-in test logic) and parameters describing the BILBO modules. Thus, a computer-aided optimization of a self-testing structure with respect to area/speed criteria can be performed without the necessity of laying out multiple self-testing versions of the original design and running timing simulation on each one.