Increasing levels of process variation in current technologies have a major impact on power and performance, and result in parametric yield loss. In this work we develop an efficient gate-level approach to accurately estimate the parametric yield defined by leakage power and delay constraints, by finding the joint probability distribution function (jpdf) for delay and leakage power. We consider inter-die variations as well as intra-die variations with correlated and random components. The correlation between power and performance arise due to their dependence on common process parameters and is shown to have a significant impact on yield in high-frequency bins. We also propose a method to estimate parametric yield given the power/delay jpdf that is much faster than numerical integration with good accuracy. The proposed approach is implemented and compared with Monte Carlo simulations and shows high accuracy, with the yield estimates achieving an average error of 2%.

Significant acceleration of todays complex collaborative design processes can be achieved if team members are able to apply search heuristics that consider the simultaneous effect of all design constraints. We present the Active approach to Design Process Management (ADPM), whereby designers receive constraint-based feedback that enables them to apply these search heuristics effectively. To evaluate ADPM, we developed a design process evaluation environment called TeamSim. Evaluation results suggest that ADPM can reduce costly design iterations at the expense of extra, less costly, verification tool executions.

Conceptual design, the preliminary phase of design in which both well-defined problem specifications and high level design solutions are developed, is becoming increasingly important as design complexity increases. In spite of the importance of this activity, few tools exist to support this phase of design. In this paper we present a systematic and flexible model of conceptual design and describe how this model has been employed to realize a prototype conceptual design process management environment, called Clio II.

Today's complex design processes feature large numbers of varied, interdependent constraints, which often cross interdisciplinary boundaries.Therefore, a computersupported constraint management methodology that automatically detects violations early in the design process, provides useful violation notification to guide redesign efforts, and can be integrated with conventional CAD software can be a great aid to the designer.We present such a methodology and describe its implementation in the Minerva II design process manager, along with an example design session.

Today's complex leading-edge design processes require the use of multiple CAD tools that operate in multiple frameworks making management of the complete design process difficult. This paper introduces the concept of framework encapsulations: software wrappers around complete CAD frameworks that allow the design data and flow management services of a framework to be utilized by a common design process management tool. This concept has been applied to the Minerva II Design Process Manager, enabling Minerva II to manage the design process across multiple CAD frameworks, and potentially multiple design disciplines.

Task management involves task creation and execution. These are facilitated using a task schema as exemplified in the Hercules Task Manager. Experience with Hercules has shown the task schema to be very useful for task creation, but less than ideal for task resolution, i.e., the selection of tool and data resources to be used in execution. Tool/data interactions often lead to resource selection constraints that cannot be captured using dependency relationships in the schema. We have addressed this by adding conditions to the task schema which use task-level meta-data to constrain resource selection. With examples we show that condi-tions are useful for handling a wide variety of real constraints. 1.

A language for defining design discipline characteristics is proposed.Design discipline characteristics such as abstraction levels, design object classifications and decompositions, design objectives, and design methodologies can be defined in a simple machine and human readable form.The language, DDDL, has led to the development of a user interface for Minerva II, a design process management tool, which, when configured with a design discipline description, can be used to aid teams of designers in the solution of complex multi-disciplinary design problems.DDDL and user interface examples are presented.

In this paper we present a formalism that allows for a complete and general characterization of design disciplines and for a unified representation of arbitrarily complex design processes taking place in the context of these disciplines. This formalism has been used as the basis for the development of several prototype CAD meta-tools that offer effective design process planning and management services.

IC manufacturing process variations are typically expressed in terms of joint probability density functions (jpdf's) or as worst case combinations/corners of the device model parameters. However, since device models can only provide approximations to actual device behavior, the difference between the two being the modelling error only a part of the measured variation in device behavior can be modelled using device model parameter variations and the remaining appears as modelling error variation. In this paper we present a novel statistical parameter extraction methodology that accounts for the effect of modelling error on device model parameter statistics and can be used to quantify the statistical suitability of conventional MOS device models.

In the Fall of 1991, after approximately two years of development, the department of Electrical and Computer Engineering (ECE) at Carnegie Mellon University (CMU) implemented a new curriculum that differed radically from its predecessor. Key features of this curriculum include: Engineering in the Freshman year, a small core of required classes, area requirements in place of most specific course requirements, mandated breadth, depth, design, and coverage across ECE technical areas, a relatively large fraction of free electives, and a single integrated Bachelor of Science degree in Electrical and Computer Engineering. In this paper we review the design of this curriculum, including a taxonomy of problems we needed to address, and a set of general principles we evolved to address them. The new curriculum is described in detail, including new data from an ongoing analysis of its impact on students' curricula choices.>

Workflow management encompasses a set of tools and techniques for organizing, monitoring, and automating complex processes. In this paper, we present an approach to applying workflow management techniques to design processes. Our approach is based upon a novel information model, called a task schema, that classifies the various tool and data objects used in a design process, and defines the rules by which tools and data may be used to form tasks. The schema-based approach to workflow management has been implemented in a CAD tool named Hercules.>

A yield maximization methodology, called the linearized performance penalty (LPP) method, that uses a penalty function as its objective is introduced. The penalty function formulation allows the integration of the goals of circuit performance improvement and yield maximization. It is computationally efficient since the objective function can be evaluated with the computational effort of about one circuit simulation. Also, a simple, yet effective, method to account for operating point variations is introduced. The effectiveness of the LPP method is illustrated through several circuit examples.

This paper presents a new approach to 3-dimensional thermal simulation of arbitrary electronic systems.This approach is based on the combination of numerical (finite elements and finite differences) and analytical (Fourier series) techniques which are very general and extremely efficient.Complex electronic systems (monolithic IC's, multichip modules, including their packaging) can be analyzed in minutes on PC's to produce a detailed temperature distributions within the system structure.The software system, MON-STR, has been developed and applied to several industrial examples.The results of this analysis are directly entered to the circuit simulator, HSPICE, as the actual temperature for each circuit element and thus an integrated electro-thermal simulation is performed.

Many CAD frameworks now use the notion of a design $OW to help provide methodology management services.MostJow-based approaches are limited, however, in that they involve a jixed sequence of operations specified in advance, restrict designers to using only those J70WS, and "hardwire" specifi tools to flows.To overcome this, we introduce the concept of "dynamically defined flows" as tool-independent$ows that are built up, on demand, by designers.Dynamically de$ned Jews can be used to provide a semantically rich means for browsing the &sign history database as well as to provide support for multiple design approaches, such as goal-based, tool-based, data-based and plan-based design.

A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. The authors extend this formulation to a more general IC quality measure. A general IC quality optimization method, significantly more efficient than Taguchi's, is introduced. This method can handle multiple performances and perform yield maximization as a special case. The optimization method is demonstrated on several circuit examples.>

The authors introduce a novel information model for CAD task management, called the task schema, that unifies many of the requisite features for data, process, and methodology management into a single, concise representation. The task schema based approach has been implemented in the Hercules task management system. Unlike previous approaches to task management, in which tasks are defined on demand, or serve as the end representations in and of themselves, Hercules uses a graphical interface to derive tasks from the task schema. Both the task schema and the internal representation of tasks in Hercules have a formal basis in established methods from graph theory and database design.>

A novel formulation of the parametric yield as a surface integral on the boundary of the disturbance space acceptability region is introduced. This formulation allows the accurate and efficient estimation of yield via a Monte Carlo method which can also produce yield gradients with minimal overhead. Under mild assumptions, the surface integral based yield estimate is continuous and practically twice differentiable almost everywhere; therefore it is ideally suited for use with powerful gradient-based optimization algorithms. A general IC quality optimization method, significantly more efficient than Taguchi's method, is also introduced. This method can handle multiple performances and handles yield maximization as a special case.>

A distributed control mechanism for a large number of VLSI CAD tools is presented. This design framework testbed, named Cadweld, simplifies designer interaction with individual CAD tools and allows arbitrary CAD tools to be easily added or deleted from the design framework. This approach is fundamentally different than many other design framework initiatives that are more concerned with providing a distributed and general data model and tools to support that model. An object-oriented tool integration methodology that treats the tools as objects is presented. This approach simplifies CAD tool control within a design framework, making the framework more general, easier to use, and more capable of supporting a large population of CAD tools. As Cadweld directly extends the unique work of the ULYSSES design framework, the ULYSSES system's strengths and weaknesses are summarized.>

Both direct and adjoint methods are applied to the computation of time-domain transient sensitivities in the already efficient SPECS piecewise approximate circuit simulation environment. By exploiting the event-driven nature of SPECS, the computation, storage, and interpolation of the Jacobians that specify the appropriate linearized circuit during the forward simulation is not required to obtain sensitivities. Both direct and adjoint methods require only a marginal computational overhead and provide equivalent results. The choice of the method to use depends on the ratio of the number of outputs to the number of parameters. More parameters favor the adjoint method and more outputs favor the direct. The overall efficiency of both SPECS and its time-domain sensitivity extension allows it to be applied to realistic circuits that, due to their large size, had previously made such analysis impractical. Simulation results on industrial circuits of up to 1500 MOS transistors show that transient sensitivities can be efficiently computed for large circuits.>

The authors describe a practical methodology that can be applied to optimize the process yield of IC fabrication lines. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrate through a simulation example involving a CMOS process adopted from an industrial line.>

An efficient methodology for performing fault simulation experiments as part of an IC failure diagnosis system is described. The methodology uses regression models that relate IC performance directly to process disturbances inherent in all IC fabrication processes. An efficient algorithm for establishing the structure of such models based on data obtained from coupled process and circuit simulators is developed. It selects a minimum number of significant input parameters and automatically establishes an optimum order polynomial regression model. Moreover. the regression models obtained contain information about the structure of the dependence of IC performances on the process disturbances, which can be coded in a dependency tree for each IC performance and used directly for diagnostic purposes. The algorithm belongs to the class of artificial neural network approaches and has been implemented in a program called MULREG (multilayer regression). Two examples of analyzing MULREG are given.>

A method is described for estimating the yield and yield gradient based on a priori geometric approximation of the acceptability region in the disturbance space. Circuit performance macromodeling is used to construct the acceptability region approximation. While yield evaluation can be carried out in either the performance space or parameter space, it is shown that for monolithic integrated circuits, the gradient of yield can only be estimated accurately in the disturbance space.>

As VLSI design frameworks evolve, a distributed control mechanism for CAD tools has become a central research issue. In this paper, we present an object oriented tool integration methodology that treats the tools as objects. This approach simplifies CAD tool control within a design framework making the framework more general, easier to use, and more capable of supporting a large population of CAD tools.

Behavioral synthesis tools generate a wide range of designs, not all suited to one layout style. Thus there is a need for a flexible framework for mapping behavioral synthesis output onto module generators and layout tools. LASSIE provides this flexible framework and introduces a structural binding step that adapts the output of behavioral synthesis tools to different layout styles. The design process is divided into structural binding, partitioning, placement, and layout generation. Several options are provided at each step, and feedback is provided to the user to allow him to evaluate the results of each step.

As the complexity of the VLSI design process grows, it becomes increasingly more costly to conduct design in a trial-and-error fashion because the number of possible design alternatives, as well as the cost of a complete synthesis and fabrication cycle, increase dramatically. A conceptual design addresses this problem by allowing the designer to conduct initial feasibility studies, giving guidance on the most promising design alternatives with a preliminary indication of estimated performance. The authors describe a general framework that supports this conceptual design and a particular instance of such a framework, called Yoda, that supports the conceptual design phase for digital signal processing filters.>

A practical methodology that can be applied to optimize the process yield of IC fabrication lines is described. The yield maximization problem is first reformulated into a deterministic design centering problem. Macromodeling and problem decomposition are then applied to solve the design centering problem efficiently. The effectiveness of this methodology is illustrated through a simulation example involving a CMOS process adopted from an industrial line.>

Transient sensitivity computation in SPECS (simulation program for electronic circuits and systems), which provides a unique capability both to enhance efficiency and to validate simulation results, is described. By using transient sensitivities with respect to the entries of piecewise constant (table) element models and suppressed parasitics, an initially crude and correspondingly quick simulation can be undertaken and then augmented if necessary for improved accuracy. More specifically, table models are refined and parasitics reintroduced only where required in the final analysis as indicated by sensitivity results. This overall approach increases confidence in the results of the SPECS simulation strategy which relies heavily on simplified models for its enhanced efficiency.>

Ulysses is a VLSI computer-aided-design (CAD) environment that effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows for the integration of a collection of individual CAD tools into a design automation (DA) system that will execute a codified design methodology. Ulysses can track the multiple partial designs that result during a complete design cycle. Furthermore, Ulysses allows the designer to interrupt the design process at any time and take control. An example involving a silicon compilation task is presented to illustrate the ability of Ulysses to execute a sequence of CAD tools automatically to generate a viable layout for an IC. This example also illustrates Ulysses' ability to recover from CAD tool failures that may result if a layout cannot be completed due to routing channel congestion or overconstrained leaf-cell boundary conditions.>

An efficient macromodeling approach for statistical IC process design based on experimental design and regression analysis is described. Automatic selection of the input variables is done as part of the model-building procedure to reduce the problem dimension to a manageable size. The resulting macromodels are simple analytical expressions describing the device characteristics in terms of the fundamental process variables. The validity and efficiency of the macromodels obtained by the approach are illustrated through their use in an IC process design centering example. Although the approach has only been applied to the IC fabrication process level, the underlying methodology can also be used to obtain circuit-level macromodels.>

Predictive subset testing is based on a statistical model of parametric process variation. In this Monte Carlo approach, a statistical process simulation, coupled with circuit simulation, is used to determine the joint probability distribution of a set of circuit performances. By evaluating the joint probability distribution, rather than assuming the performances to be independent, correlations that exist between them can be exploited and the number of performances that need to be explicitly tested can be reduced. Once a subset of performances for explicit testing has been identified, regression models for the untested performances are constructed, and, from the confidence intervals, limits are assigned for the tested performances. In this manner, the values of the untested performances can be predicted, reducing test complexity and cost.>

An efficient macromodeling approach for statistical IC process design based on experimental design and regression analysis is described. Automatic selection of the input variables is done as part of the model building procedure to reduce the problem dimension to a manageable size. The resulting macromodels are simple analytical expressions describing the device characteristics in terms of the fundamental process variables. The validity and efficiency of the macromodels obtained by the approach are illustrated through their use in an IC process device design centering example.>

Ulysses is a VLSI CAD environment which effectively addresses the problems associated with CAD tool integration. Specifically, Ulysses allows the integration of CAD tools into a design automation system, the codification of a design methodology, and the representation of a design space. Ulysses keeps track of the progress of a design and allows exploration of the design space. The environment employs artificial intelligence techniques, functions as an interactive expert system, and interprets descriptions of design tasks encoded in the scripts language. An example of an integrated circuit layout design task is provided. The use of Ulysses in performing this task is discussed in detail.

The use of simulation tools to verify the behavior of integrated circuits is a well established technique for circuit design. This paper describes a novel approach for circuit simulation that promises a significant improvement over conventional methods. The algorithm involves an explicit event driven technique that seems stable even when the accuracy of the solution is relaxed, and is able to perform automatic and dynamic partitioning of the network, thus allowing the full exploitation of latency in large digital networks. Although the basic method could be generalized for any type of circuit, in this paper the scope is limited to MOS integrated circuits.

In this paper we present a unified framework for prediction and estimation of the manufacturing yield of VLSI circuits. We formally introduce a number of yield measures that are useful both during the design process and during the manufacturing process. This framework is general enough to bridge the gap between the traditional concepts of parametric and catastrophic yield. We provide a classification of causes of yield loss which is essential for efficient yield estimation. Finally, we relate yield to manufacturing costs which provides a common denominator for the discussion of the manufacturing process efficiency.

Worst-case analysis is one of the most often used techniques for verifying that the sensitivity of integrated circuit (IC) performances to changes in manufacturing conditions is minimized. However, worst-case analysis is often carried out in terms of a correlated set of parameters, which results in a design that is unnecessarily pessimistic. This paper presents a new approach to the worst-case analysis of integrated circuits that results in more realistic estimates of variations in device and circuit performances. In particular, worst-case analysis is performed in terms of a set of statistically independent process disturbances. A software package for worst-case analysis is described and illustrated by a number of examples. The results of the proposed worst-case analysis method are compared to Monte Carlo simulations.

A global floorplanning approach is presented which allows designers to quickly explore layout issues during the initial stages of the IC design process. The approach is based on a combined mincut and slicing paradigm, in an effort to ensure routability. A slicing-tree representation is employed, upon which efficient traversal operations are applied resulting in area-efficient floorplans. The method allows modules to be specified as having a number of possible dimensions, and considers I/O pads as well as layout constraints. As a global improvement over previous floorplanning efforts, an in-place partitioning scheme is applied in conjunction with a combined exhaustive and heuristic bipartitioning approach. Moreover, a global channel routing and module I/O pin assignment scheme is used for floorplan evaluation, whereby module dimensions are chosen in conjunction with routing area, ensuring compact floorplans. A computer program, Mason, is presented which efficiently implements the approach and provides an interactive environment for designers to perform floorplanning. The performance of the program is discussed in terms of several industrial examples.

It is well known that the integrated circuit (IC) manufacturing process is subject to inherent statistical fluctuations of material quality and equipment performance. Characterization of these fluctuations is important if the performance of an IC manufacturing facility is to be simulated and optimized. In this paper we present a general methodology for determining the statistical moments associated with a set of independently varying parameters, that are principally responsible for the fluctuations in the IC manufacturing process. This methodology has been implemented in a program called PROMETHEUS. A method for the formal statistical verification of the extracted moments is also presented.

This paper describes the yield simulator VLASIC (VLSI Layout Simulation for Integrated Circuits). VLASIC is a Monte Carlo simulator that uses defect models and statistics to place random catastrophic point defects on a chip layout and determine what circuit faults, if any, have occurred. The defect models are described in tables, and so are readily extended to new processes or defect types. The defect statistical model is based on actual fabrication line data, and has not appeared before in the literature. The circuit fault information generated by VLASIC can be used to predict yield, optimize design rules, generate test vectors, evaluate redundancy, etc. A redundancy analysis system which uses these data is described, and an example of its use given.

This paper describes the circuit simulation algorithms of the SAMSON2 mixed circuit/logic simulator. SAMSON2 employs event driven simulation techniques to exploit the inherent temporal sparseness in VLSI circuits. At the circuit level, SAMSON2 can be more than an order of magnitude faster than a "standard" circuit simulator such as SPICE2 while providing comparable waveform accuracy. This performance is achieved by partitioning a circuit into subcircuits which are allowed to have separate integration step sizes reflecting their activity level. The accuracy of the solution is maintained by controlling the errors due to decoupling among the subnetworks as well as the local truncation within each subnetwork. Simulation examples of typical MOS integrated circuits (IC's) are presented. f

Random fluctuations which are inherent in the IC manufacturing process cause production yields to be significantly less than 100 percent. Yield drop is caused by two types of faults, catastrophic and parametric. This paper deals with the diagnosis of parametric faults which occur during the manufacturing of IC's and cause the yield to drop below some acceptable level. A statistical pattern recognition approach to IC failure analysis is developed in this paper. Identification of faults is based on the analysis of the joint probability density function of circuit performances. A number of alternative approaches to IC failure analysis are developed and their efficiency is discussed. Also a complete statistical pattern recognition system with learning capability is proposed and all the stages of its development are discussed. An efficient method for fault simulation which is based upon statistical process simulation is proposed. The performance of the algorithms proposed in this paper has been successfully verified for data collected from commercial fabrication processes and from computer simulation.

This paper describes FABRICS II, an IC fabriction process simulator which takes into account the statistical fluctuations inherent in the manufacturing process. FABRICS II is composed of two parts, a fabrication process simulator FAB1, and a semiconductor device simulator FAB2. The simulator produces model parameters of typical semiconductor devices manufactured in various fabrication processes (NMOS, CMOS, or bipolar). Possible applications of FABRICS II include verification and optimization of process and circuit design, yield prediction and maximization prior to IC fabrication, and IC failure analysis. Two examples which illustrate the application of FABRICS II are presented.

Random variations inherent in any fabrication process may result in very low production yield. This is especially true in the fabrication of integrated circuits. Several methods have been proposed to help the circuit designer minimize the influence of these random variations. Most of these methods are deterministic and try to maximize yield by centering the nominal value of the designable parameters in the so-called region of acceptability. However, these design centering techniques require an assumption of convexity which is not valid in many real design situations. To overcome this problem a new convergent method is proposed which is based on the sequential solution of subproblems for which the convexity assumption is valid. A practical implementation of the algorithm is shown by examples to be computationally efficient.