Peripheral nervous system (PNS) recording plays an essential role in the development of neural-controlled prosthetics. Compared to cortical recording, PNS requires front-end circuitry with lower input-referred noise and higher accuracy. A chopper-stabilized front-end with its transfer function set by precision capacitor ratios that meets these goals is introduced. Using a windowed integration sampling technique, the continuous-time anti-aliasing filter that usually precedes the lowpass switched-capacitor (SC) filter can be eliminated. High gain accuracy is achieved using a closed-loop switched-capacitor topology wherein a chopper-modulatedsincfunction is realized. The corner frequencies of the front-end are determined by a downstream switched-capacitor filter and a DC servo-loop-based SC integrator. The overall energy efficiency is further improved using correlated level shifting in the SC filter and integrator stages to simplify the operational amplifier topology. A positive feedback loop is also incorporated to increase the input impedance. The PNS front-end implemented in 180 nm CMOS has a gain of 58.1 dB and an integrated input-referred noise of$2.2\mu \text{V}_{\mathrm {rms}}$over the -3 dB bandwidth from 170 Hz - 9.68 kHz; the input impedance is$>$61M$\Omega $@ 1 kHz. The total harmonic distortion is -66.6 dB with a 1.8Vppoutput swing. The complete front-end including clock generation circuitry occupies 0.136 mm2, draws$16.1 \mu \text{A}$from a 1.8 V supply, and achieves a noise efficiency factor of 3.5.

Compressed sensing (CS) exploits signal sparsity in some domain to enable sub-Nyquist sampling which increases the energy efficiency of analog-to-digital conversion (ADC) and downstream data processing circuits–the sampling frequency is determined by the information rate, not the usual Nyquist rate. CS techniques for wireless multi-channel bio-signal recording applications based on sigma-delta modulation (SDM) are detailed and used to validate a multi-channel recovery algorithm. The SDM topology allows the required dot product calculations between the measurement and signal vectors to be performed in conjunction with its inherent integration using minimal additional circuitry. It eliminates opamp output saturation concerns and benefits directly from still ongoing Moore’s Law CMOS technology scaling. Finally, a sparse sensing matrix and recovery algorithm are described that exploit similar sparse signatures across multiple channels to improve both signal recovery accuracy and chip area efficiency. Simulation results validate the concepts.

The CMOS switched-capacitor power amplifier (SCPA) architecture was disclosed by S.M. Yoo, et al., in 2011 [1]-[2]. It enabled the design of fully-integrated radio frequency (RF) transmitters with much higher power-added efficiency (PAE) than previous approaches. Herein, new techniques are introduced that also increase SCPA linearity. Specifically, a new switching scheme decreases the amplitude modulation to phase modulation (AM-PM) distortion. When applied to class-G SCPAs [3]-[4], the linearity using the new switching scheme is improved significantly compared to conventional SCPA implementations. More specifically, the AM-PM non-linearity of the class-G SCPA is reduced by about ~ 4X and the error vector magnitude (EVM) is improved by ~ 3 dB.

Compressed sensing (CS) is a sampling scheme that exploits signal sparsity to reduce the digitizing rate and thus improve analog-to-digital converter (ADC) power efficiency. By decoupling the analog signal frequency and digitizing rate, the ADC sampling rate is determined by the information rate rather than the maximum signal frequency. Herein we propose a compressed sensing scheme for multi-channel bio-signal recording based on sigma-delta modulation (SDM). The dot products between the signal and measuring vectors are realized by the inherent integration of the SDM with relieved saturation concern. Compared to other CS scheme, front-end based on CS SDM scales better with continuing advances in CMOS technology. A sparse sensing matrix and modified recovery algorithm that exploits similar sparse signatures across multiple channels improve both chip area efficiency and signal recovery accuracy. Detailed analyses are validated by extensive simulation results.

The CMOS switched-capacitor power amplifier (SCPA) proposed in 2011 [1]-[2] achieved much higher system efficiency than conventional transmitter architectures. In this paper, SCPA linearity is also analyzed and improved with new techniques. Specifically, a baseband harmonic-rejection (BBHR) technique is used to minimize the counter third-order intermodulation products (C-IM3). Also, using a Wilkinson combiner, the cross-coupling between two sub-SCPAs is isolated to enable a linear harmonic-rejection summation. With the proposed topology, the linearity is improved significantly compared to a conventional I/Q-sharing SCPA. More specifically, the C-IM3 is reduced by ~25 dB with a single-tone input and by ~22 dB with modulated signal.

The gm/ID-based design of analog integrated circuits introduced by Silveira, et al. in 1996 [1] employs an empirical transistor sizing methodology using SPICE-generated lookup tables. In the design of ultra-low-power amplifiers, the iconic plots of gm/IDvs VOVsuggest that some devices should be operated deep in weak inversion (e.g., VOV≃ −0.2V) where gm/ID is near maximum. Performance parameters such as gain, bandwidth, thermal noise, power dissipation, etc., benefit from this choice. However, in applications where small-signal settling time is critical (e.g., precision switched-capacitor circuits), the unity-gain phase margin, PM, is a parameter of paramount importance. PM (i.e., small-signal settling time) vs. VOV(i.e., strong, moderate or weak inversion) design considerations are presented in this paper. The key result is that as the design choice of VOVmoves the region of operation from strong to moderate to weak inversion, PM is reduced substantially and settling time is increased dramatically. In addition to new design insights, area-efficient device layout techniques are illustrated that improve performance.

The gm/ID-based design of analog integrated circuits introduced by Silveira, et al. in 1996 employs an empirical transistor sizing methodology using SPICE-generated lookup tables that enables good agreement between simulations and specifications. A new SPICE lookup table is introduced that extends the gm/ID approach to the Miller pole-splitting frequency compensation of the classical CMOS two-stage operational transconductance amplifier (OTA) that has been in high-volume production since 1980.

A digital switched-capacitor transformer-combining power amplifier (SCPA) that uses load modulation to achieve efficiency peaking at 0, -6, and -12 dB backoff levels is beneficial for signals with high peak-to-average power ratios (PAPR). The PA uses a specific switched-capacitor cell design and turn-on sequence, that, contrary to the prior art, ensures correct-by-construction load modulation at backoff, even in the presence of practical transformer non-idealities. The PA has been implemented in 32nm CMOS and tested as part of a complete WiFi polar transmitter.

A two-stage load-pole-cancelled (LPC) operational transconductance amplifier (OTA) which consumes an order of magnitude less power than a conventional Miller-compensated OTA is described. An extra stage is added to a conventional CMOS two-stage OTA to enable LPC. The concept, validated in a 0.18 um CMOS process, achieves an ~8× power reduction compared to the conventional OTA for a load capacitance of 5 pF.

A low-noise chopper amplifier for bio-signal recording is described. Potential applications include many-electrode implantable ECG acquisition systems along with EEG, EMG and ECoG bio-signals. Designed in 0.13μm CMOS, the two-stage amplifier uses a folded cascode topology with a low-impedance node chopping technique combining both voltage and current-mode chopping for an optimal noise and bias current tradeoff while significantly reducing ripple from the 40 KHz chopper modulation signal. Experimental results show an amplifier with digitally programmable gain from 40 - 83 dB, bandwidth from 340 - 7.5 KHz and high pass cutoff of 170 mHz, while dissipating only 1.1 μW from a 1.2 V supply. The inputreferred noise is 2.1 μVrms integrated over a 100 mHz - 100 KHz bandwidth with a noise efficiency factor of 3.28.

Architectural schemes for low-power calibration of oversampled analog-to-digital (A/D) systems are presented. Conventional full-rate least-mean squares (LMS) calibration has two well-known limitations: slow convergence and increased computational complexity/power dissipation for higher adaptive filter orders and sampling frequencies. Half (fs/2) and quarter-rate (fs/4) LMS calibration for oversampled A/D decimators are used to reduce the computational complexity. Noble identities and polyphase decimation are used to implement these schemes to match digital noise-cancellation filters (NCF) to the corresponding transfer functions of an analog fourth-order cascade sigma-delta (ΣΔ) ADC. Energy savings up to 30% compared to conventional full-rate (fs) schemes are confirmed using an Altera Stratix II field programmable gate array (FPGA). The analog front-end comprises a switched-capacitor 2-2 cascade ΣΔ ADC implemented in 0.13 μm CMOS. Using differential-pair opamps with gains of only 22 db and an oversampling ratio OSR = 8, the ΣΔ ADC system achieves 11-bit accuracy over a 9.4 MHz bandwidth with SNR = 67 dB and SFDR = 75 dB.

Compressed sensing (CS) is a rapidly emerging signal processing technique that enables accurate capture and reconstruction of sparse signals from only a fraction of Nyquist- rate samples, significantly reducing the data-rate and system power consumption. This paper presents an in-depth comparative study on current state-of-the-art CS reconstruction algorithms. Reliability, accuracy, noise tolerance, computation time and are used as key metrics. Further, experiments on ECG signals are used to assess performance on real-world bio-signals.

Application of the Analog Chirp Fourier Transform (ACFT) in generating low-latency, continuous, real-time frequency spectra of wide bandwidth radio frequeny (RF) signals is presented as an alternative to the digital FFT processor. Insights into the mathematical construct of ACFT, system modeling, and practical design considerations are presented. Resolution and worst-case frequency error are key metrics evaluated over design parameter choices and process, voltage, and temperature (PVT)-induced parameter variations. Experiments show accurate frequency spectrum representation over several decades extending from 200 MHz to 6 GHz with a 58 MHz worst-case resolution and 1 μs latency.

Sub-Nyquist analog pre-processing of sparse signals is achieved using the emerging compressed sensing (CS) signal processing paradigm. Electrocardiogram (ECG) signals have been shown previously to have significant time-domain sparsity. It is shown herein that electromyogram (EMG) signals exhibit both time and frequency-domain sparsity. Hence, CS techniques are advantageous in either domain in reducing the energy consumption in an adaptive data acquisition front-end that is part of a body area network (BAN). A measurement matrix of random values is central to CS computation. Signal-to quantization-noise ratio (SQNR) results with EMG signals show that 6-bit (including sign) Gaussian random coefficients are sufficient for compression factors up to 18X. It is also shown that 6-bit uniform random coefficients are preferred for some EMG bio-signals.

A fully-integrated LNA in 0.18/xm CMOS simultaneously achieves high gain, low noise figure (NF), good third-order input intercept linearity (IIP3), and low DC bias current consumption: 19 dB, 2.4 dB, -14.2 dBm and 1.3 mA, respectively, from a 1.2 V supply. The single-ended LNA uses a common-gate common-source (CG-CS) topology and operates at 5.4 GHz for WLAN applications. Using gm-boosting, current-reuse and transformer-feedback techniques, the LNA mitigates several design issues seen in the widely used common-source common-source current-reuse (CS-CS) LNAs and improves the IIP3 of CG-CS schemes by 6 dB, without increasing power and area consumption.

Wireless local area network (WLAN) transmissions in the 5-6 GHz band pose severe desensitization problems for UWB receivers. This paper describes a concurrent Mode-I (3.17-4.75 GHz) and Mode-III (6.34-7.92 GHz) UWB low-noise amplifier (LNA) employing a wideband filter with a tunable notch that attenuates WLAN blockers. Specifically, the notch attenuation and gain are tunable over a wide range. The gain is enhanced using wideband feedback and is programmable from 9-14.5 dB. Simultaneously, blocker attenuation of 10-20 dB over the WLAN frequency band is achieved. Implemented in a 0.13-μm CMOS process and operated with 4.8 mA bias current, the LNA achieves a NF of 4.3-5.1 dB and a minimum IIP3 of -1.1 dBm.

An area-efficient U-shaped slow-wave coplanar waveguide (U-SCPW) in a standard 0.18 μm CMOS process is presented. Compared to a conventional straight line CPW (S-CPW), it provides a more compact layout because of its approximate 1:1 aspect ratio. Measured results show that it has a quality factor and phase velocity comparable to its straight-line counterpart with measured Q ~ 30 at 23 GHz.

As CMOS technologies and their respective supply voltages continue to scale downwards, new methods for designing RF analog and mixed-signal circuits must be found. A promising technique that has emerged is the use of monolithic transformers. Unfortunately, due to parasitic magnetic coupling, there can be a substantial amount of cross-talk between transformers and other, nonrelated, devices resulting in the requirement for large separation distances and hence, wasted silicon. This paper presents a new winding scheme that reduces the parasitic magnetic coupling by approximately 1000X (32 dB) and allows the separation distance between transformers to be reduced by 10X.

Dynamic spectrum access (DSA) is a promising approach for the more effective use of existing spectrum. Of fundamental importance to DSA is the need for fast and reliable spectrum sensing over a wide bandwidth. A model for two-stage sensing is described based on an analysis of the mean time to detect an idle channel. Simulation results show that it provides significantly faster idle channel detection than conventional single-stage random searching. Several system-level issues are also investigated including the settling time of the phase-locked loop (PLL) in the frequency synthesizer, which determines the channel switching time. Effects of the bandwidth of the coarse sensing block and the integration duration of the energy detector are also presented.

The origins and detrimental effects of charge injection in charge-pump PLLs are discussed. Standard topologies for minimizing charge injection are discussed, and a new charge- pump topology with virtually zero charge injection is presented. Simulation results are presented to compare the performance of the proposed topology with standard designs, and it is shown that the new topology minimizes the steady state phase offset.

Approaches for modeling continuous-time (CT) SigmaDelta modulators based on the Bilinear (BT), Lossless-Discrete Integration (LDI) and Impulse Invariant (II) transformations are compared for low-OSR cascade architectures. A hybrid modeling approach is introduced that combines the BT and LDI transformations, and enables direct synthesis of the CT modulator from a discrete-time (DT) template. The resulting CT architecture is identical to the DT counterpart; i.e., no new signal paths are introduced. Moreover, frequency warping is not required as in the BT case for low-OSR modulators.

A parallel, multi-resolution spectrum sensing technique that is amenable to multiple-antenna cognitive radios is introduced. The authors show that for energy-detector-type spectrum sensors, the total sensing time due to FFT latency is reduced by 100 times using the proposed method versus the fixed-resolution, serial detection method employed in single-antenna systems. System-level tradeoffs such as the number of antennas, sensing bandwidth, and FFT size are also explored.

A new sigma-delta architecture employs feed-forward topology with digital summing. The feed-forward architecture reduces the signal swings of the integrators and hence modulator distortion while digital summing eliminates the need for a summing op-amp and makes the design more robust to comparator offsets. Applying this architecture to a 2-2 cascade ADC, we can achieve a 12b resolution over a 10MHz signal bandwidth with a sampling rate of 160 MSamples/sec. The topology is especially attractive for low-power and low-voltage applications.

A method to design spiral transformers is outlined. It utilizes simple inductance estimates in order to initially design the dimensions for the desired transformer, after which an EM simulation is used to extract s-parameters of the structure; a compact model is then extracted from the s-parameter results. A wideband compact model is proposed that is accurate up to the self-resonance frequency (SRF) of the structure. A 3-to-1 transformer is designed and its measured performance verified in a 0.18 μm RF CMOS process.

A delay generation technique applied to loop-bandwidth enhancement of frequency synthesizers is proposed for faster switching. PMOS transistors are used to provide large resistances and a diode-connected PMOS device generates the switch gate-bias voltage to reduce delay variations over process. An integer-N PLL employing the above technique for bandwidth enhancement is designed and simulated at 2.4GHz. It has a phase noise of -123dBc/Hz @ 1MHz offset. The lock time is 40mus, and the tuning range is 200MHz

An analysis of reflective-type phase shifters with transformed single-resonant loads is presented. Several components of the standard lumped-element coupler can be eliminated without significant performance degradation, to allow more compact implementations. A reflective-type phase shifter operating at 2.0 GHz has been designed in a 0.18 mum CMOS process, occupying an area of 0.75 mm2and consuming 5.4 mW of power. Simulations have been performed on the extracted circuit, including all resistive and capacitive parasitics. The phase shift range is 338deg for a control voltage range from 0-1.8 V, and 675deg for 0-2.5 V. The maximum loss and noise figure are -10 dB and 19 dB, respectively, over the control voltage range from 0-1.8 V

An analysis of the noise performances of the current steering and simple cascode variable gain amplifier topologies is presented. Simulation results are used to determine the dominant noise sources at reduced gain levels, and analytical techniques are used to obtain a sizing strategy for minimizing the overall noise figure. The optimum configuration is shown to be a current steering topology with unequal sizing for the current steering transistors. Using simulations for the final sizing optimization, a current steering variable gain amplifier has been designed in 0.18 mum CMOS technology. The amplifier consumes 8 mW of power, has a maximum S21 of 20.6 dB, a noise figure of 1.47 dB at the maximum gain, and a noise figure of 8.8 dB when the gain is reduced by 20 dB

A phase feedback architecture is proposed which allows the phase of each path in a multiple antenna system to be set quickly and accurately. The feedback action of the proposed system will adjust the phase to compensate for errors caused by changes in operating conditions. The central component of the proposed architecture is a variable-offset phase detector. An architecture for this block is presented, which uses a digital input to achieve programmable phase offsets from 0deg to 180deg. The circuit has been simulated in 0.18 mum CMOS technology, and its operation has been demonstrated at frequencies up to 3 GHz with a power consumption of 0.95 mW

The analysis and design of lumped-element quadrature directional couplers is described for monolithic applications. The analysis is carried out using the fourfold symmetry of capacitively and inductively coupled hybrid circuits. S-parameter responses of these two types of couplers are compared when losses and other parasitic effects of typical on-chip passive elements are taken into account. The analysis provides analytical expressions that make it possible to determine the effects that each non-ideality has on overall circuit performance before circuit simulations are performed using a particular process design kit

A fully integrated 5-6GHz differential VCO derived from the classical Clapp topology is presented in 180nm CMOS. The Clapp architecture and its characteristics are reviewed, and the location of critical portions of the circuit such as the LC-tank and varactors is discussed. The use of a Clapp VCO topology allows a larger voltage swing, which improves spectral purity and phase noise. The use of a symmetrical inductor for differential operation results in a higher Q with lower area, while providing common-mode noise rejection. The VCO achieves a simulated phase noise of -98dBc/Hz @ 100kHz & -123.1dBc/Hz @ 1MHz offsets, and draws 5mA from a 1.8V power supply. A high tuning range of 18% and FOM of 189dBc/Hz are reported. Finally, system-level simulations of a frequency synthesizer for the IEEE 802.11a bands using the Clapp VCO are presented

Issues related to substrate noise in system-on-chip design are described including the physical phenomena responsible for its creation, coupling transmission mechanisms and media, parameters affecting coupling strength, and its impact on mixed-signal integrated circuits. Design guidelines and best practices to minimize the generation, transmission, and reception of substrate noise are outlined, and different modeling approaches and computer simulation methods used in quantifying the noise coupling phenomena are presented. Finally, experiments that validate the modeling approaches and mitigation techniques are reviewed

An RF IC optimization methodology based on an elitist distributed particle swarm optimization algorithm is presented. By including a Pareto ranking mechanism and elitism in the algorithm, design alternatives and tradeoff information are provided with high efficiency. Post-optimization Monte-Carlo simulations are performed to assess first-order yield performance and aid in the selection of the final design. The approach is validated through the synthesis of a 5.2GHz direct-conversion front-end in 180nm CMOS.

A hierarchical divide-and-conquer multi-optimization methodology for phase-locked loop synthesis is presented. By optimizing each building block in the PLL separately with various optimization techniques, high optimization efficiency and good circuit performance are achieved. The methodology is validated with the synthesis of a 1GHz third-order PLL in 240nm SiGe BiCMOS.

A custom CAD synthesis tool based on particle swarm optimization, and results from the design of an RF CMOS distributed amplifier optimized to overcome non-idealities associated with parasitic-laden passives, are presented. The particle swarm synthesis approach is shown to be more than an order of magnitude faster than the simulated annealing design and optimization algorithm.

No abstract available.

A quiet logic family-complementary metal-oxide-semiconductor (CMOS) current steering logic (CSL)-has been developed for use in low-voltage mixed-signal integrated circuits. Compared to a CMOS static logic gate with its output range of /spl Delta/V/sub logic//spl ap/V/sub dd/, a CSL gate swings only /spl Delta/V/sub logic//spl ap/V/sub T/+0.25 V because the constant current supplied by the PMOS load device is steered to ground through either an NMOS diode-connected device or switching network. Owing to the constant current, digital switching noise is 100/spl times/ smaller than in static logic. Another useful feature which can be used to calibrate CSL speed against process, temperature, and voltage variations is propagation delay that is approximately constant versus supply voltage and linear with bias current. Several CSL circuits have been fabricated using 0.8 and 1.2 /spl mu/m high-V/sub T/ n-well CMOS processes. Two self-loaded 39-stage ring oscillators fabricated using the 1.2 /spl mu/m process (1.2 V power supply) exhibited power-delay products of 12 and 70 fJ with average propagation delays of 0.4 and 0.7 ns, respectively. High-V/sub T/ and low-V/sub T/ CSL ALU's were operational at V/sub dd//spl ap/=0.70 V and V/sub dd//spl ap/0.40 V, respectively.

Algorithms for the efficient evaluation of substrate parasitics in mixed-signal integrated circuits have been developed and incorporated in an extraction tool for substrate parasitics, SUBTRACT. Using a preprocessed, polynomial-based boundary element method, SUBTRACT enables the parasitic extraction process to be completely technology independent, allowing for fast evaluation. Additionally, techniques to accelerate the iterative solution of the resulting impedance matrix have been developed and employed to further improve the speed advantages that this method offers. The preprocessed boundary element method is more efficient than finite-difference schemes and orders of magnitude faster than general boundary element methods using a direct evaluation of Green's function. Results of employing SUBTRACT to the design and verification of a mixed-signal A/D converter IC are described.

A low-power high-speed architecture for /spl Sigma/-/spl Delta/ modulators is proposed. Results are presented for a first-order /spl Sigma/-/spl Delta/ modulator constructed using a low-power fully-differential current-mode continuous-time integrator with a sampling frequency of 128 MHz. Deleterious effects due to glitches associated with the feedback D/A converter are circumvented through simple modifications of the system-level timing. The results are in good agreement with the theoretical limits: for an oversampling ratio of 128, behavioral simulations predict a maximum dynamic range of 56.9 dB for an input signal amplitude of -3 dB. Power dissipation for the first-order /spl Sigma/-/spl Delta/ modulator is 1 mW in a 1.2 /spl mu/m CMOS process with a 3.3 V power supply.

Proposed in this paper are two key components for a magnetic recording channel detection system: a continuous-time current-mode forward equalizer and a sample-and-hold current-mode backward equalizer. Both are designed for use with the Fixed Delay Tree Search with Decision Feedback (FDTS/DF) detection algorithm. The forward equalizer architecture consists of a bank of bandpass and allpass filters. The backward equalizer uses current steering principles to implement a high-speed robust architecture. Simulations show that an FDTS system utilizing the proposed forward equalizer architecture has performance equivalent to that of a system including an FIR equalizer with 24 taps. A transresistance integrator and transconductance amplifier are used to realize a current-mode, variable-gain integrator building block. This building block is used to implement the tunable bandpass and allpass filters in the equalizer. Simulations based on a 0.8 /spl mu/m CMOS process show that the forward equalizer is tunable up to 82 MHz. For a given FDTS/DF detection scheme utilizing 2/3(1,7) coding, this translates into approximately 130 to 164 Msamples/s. The corresponding power dissipation is 86 mW from a 3 V power supply. Simulation of the backward equalizer indicates a maximum operating-speed of approximately 100 Msamples/s.

The design and application of low power VLSI-based circuits and systems is the focus of this forum and paper. Attention is placed on issues related to low power systems, such as choice of implementing semiconductor technology, power supply voltage (e.g., 3.3 V, 2.5 V, 1.0 V), CAD for low power design and synthesis, micropower digital and analog circuit design techniques, system architectural tradeoffs for low power, selective clocking for power management, low power synchronization strategies, self-calibration circuit techniques for low power, and low power figures of merit.>

The incomplete Choleski conjugate gradient (ICCG) method and a macromodeling technique employing asymptotic waveform evaluation (AWE) have been applied to the simulation of integrated circuits in the presence of parasitic electrical and thermal substrate coupling interactions. Simulation of electrical substrate coupling effects has been found to be accurate and fast as compared to MEDICI, a device simulation program. Simulation results are also in good agreement with reported measurements on a test chip fabricated in a 2/spl mu/m BiCMOS n-well process. DC/steady-state and transient simulations of thermal substrate interactions using similar techniques on several benchmark circuits show orders of magnitude reduction in cpu time compared to traditional simulation techniques.