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R. Timothy Edwards

dblp:91/3227 · DBLP profile ↗
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7ranked-venue papers
4as first author
0since 2021 · last 2002
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Artificial intelligence and machine learning · 5 · 3 first-authorSystems, architecture and hardware · 1 · 1 first-authorGraphics, computer vision, multimedia, augmented reality and games · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
2 papers
Hardware accelerators and domain-specific architectures · 51% Integrated circuit design · 34% Performance modeling and evaluation · 15%
Computer graphics and multimedia
2 papers
Audio and music processing · 79% Image and video processing · 21%

Topics — the 3 heaviest of 5, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware accelerators and domain-specific architectures
correlation technique
0.011998
Optimizing Correlation Algorithms for Hardware-Based Transient Classification · NIPS 1998
Integrated circuit design › analog and mixed-signal circuits
analog VLSI
0.011995
Analog VLSI Processor Implementing the Continuous Wavelet Transform · NIPS 1995
Image and video processing
wavelet transform
0.011995
Analog VLSI Processor Implementing the Continuous Wavelet Transform · NIPS 1995

Methods — techniques the papers use, named apart from their topics

analog VLSI · 0.0correlation algorithm · 0.0signal processing · 0.0
YearPublicationVenuePosition
2002 Neuromorphic processor for real-time biosonar object detection
abstract
Real-time classification of objects from active sonar echo-location requires a tremendous amount of computation, yet bats and dolphins perform this task effortlessly. To bridge the gap between human-engineered and biosonar system performance, we developed special-purpose hardware tailored to the parallel distributed nature of the computation performed in biology. The implemented architecture contains a cochlear filterbank front-end performing time-frequency feature extraction, and a kernel-based neural classifier for object detection. Based on analog programmable components, the front-end can be configured as a parallel or cascaded bandpass filterbank of up to 34 channels spanning the 10 to 150 kHz range. The classifier is implemented with the Kerneltron, a massively parallel mixed-signal Support Vector “Machine” in silicon delivering a throughput in excess of a trillion (1012) multiply-accumulates per second for every Watt of power dissipation. The system has been evaluated on detection of mine-like objects using linear frequency modulation active sonar data (LFM2, CSS Panamy City), achieving an out-or-sample performance of 93% correct single-ping detection at 5% false positives, and a real-time throughput of 250 pings per second.
Gert Cauwenberghs, R. Timothy Edwards, Yunbin Deng, Roman Genov, David Lemonds
ICASSP2
2000 A field-programmable mixed-signal array architecture using antifuse interconnects
abstract
Field-programmable gate arrays (FPGAs) have been a great boon to the electronics industry, facilitating rapid and reliable prototyping of digital systems at low cost. Radiation-tolerant versions have had a major impact on space industries where low volume and the requirement of flight qualification makes custom ASIC design an expensive option, with slow development cycles. Presently, custom ASIC or discrete component design are the usual options for analog and mixed-signal circuit design, FPAA (Field-Programmable Analog Array) and FPMA (Field-Programmable Mixed-signal Array) parts exist but tend to be rather specialized in function, and none exist in radiation-tolerant form for use in aerospace applications. This paper outlines an architecture proposed for an FPAA fabricated in an existing commercial digital CMOS process used to make radiation-tolerant antifuse-based FPGA devices. The primary concerns are the impact of the technology and the overall array architecture on the flexibility of programming, the bandwidth available for high-speed analog circuits, and the accuracy of the components for high-performance applications.
R. Timothy Edwards, Kim Strohbehn, Steven E. Jaskulek
ISCAS1
1999 AdOpt: analog VLSI stochastic optimization for adaptive optics
abstract
Phase distortion in wavefront propagation is one of the key problems in optical imaging and laser optics applications. We present a hybrid VLSI and optical system for real-time adaptive phase distortion compensation. The system operates "model-free", independent of the specifics of the distorting optical medium and the compensation control elements. Our VLSI system implements stochastic parallel perturbative gradient descent/ascent so that we achieve fast optimization of the chosen performance metric to achieve real-time compensation. We include experimental results of the hybrid VLSI-optical system demonstrating successful operation for a laser-beam focusing/defocusing task.
Marc Cohen, R. Timothy Edwards, Gert Cauwenberghs, Mikhail A. Vorontsov, Gary Carhart
IJCNN2
1999 Acoustic Transient Classification with a Template Correlation Processor
abstract
I present an architecture for acoustic pattern classification using trinary-trinary template correlation. In spite of its computational simplicity, the algorithm and architecture represent a method which greatly reduces bandwidth of the input, storage requirements of the classifier memory, and power consumption of the system without compromising classification accuracy. The linear system should be amenable to training using recently-developed methods such as Independent Component Analysis (ICA), and we predict that behavior will be qualitatively similar to that of structures in the auditory cortex.
R. Timothy Edwards
Int. J. Neural Syst.1
1998 Optimizing Correlation Algorithms for Hardware-Based Transient Classification
R. Timothy Edwards, Gert Cauwenberghs, Fernando J. Pineda
NIPS1
1996 Bangs, Clicks, Snaps, Thuds and Whacks: An Architecture for Acoustic Transient Processing
Fernando J. Pineda, Gert Cauwenberghs, R. Timothy Edwards
NIPS3
1995 Analog VLSI Processor Implementing the Continuous Wavelet Transform
R. Timothy Edwards, Gert Cauwenberghs
NIPS1