Demo Data from EDBT 2026 / reviewers in the wild / expert
Werner Grass
dblp:91/3367
· DBLP profile ↗
14ranked-venue papers
8as first author
1since 2021 · last 2022
0000-0002-4388-5203ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 12 · 7 first-authorSoftware engineering, systems software and programming languages · 1Human-computer interaction and ubiquitous computing · 1 · 1 first-authorTheory of computation · 1 · 1 since 2021
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
3 papers |
Electronic design automation · 84% Integrated circuit design · 8% Storage systems · 8% |
Topics — the 6 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
design space exploration |
0.0 | 1 | 1990 | Global Hardware Synthesis from Behavioral Dataflow Descriptions · DAC 1990 |
Electronic design automation
high-level synthesis |
0.0 | 1 | 1990 | Global Hardware Synthesis from Behavioral Dataflow Descriptions · DAC 1990 |
Electronic design automation
physical design |
0.0 | 1 | 1982 | A depth-first branch-and-bound algorithm for optimal PLA folding · DAC 1982 |
Electronic design automation › logic synthesis › logic optimization
PLA folding |
0.0 | 1 | 1982 | A depth-first branch-and-bound algorithm for optimal PLA folding · DAC 1982 |
Storage systems
incremental update |
0.0 | 1 | 1980 | Optimization of the influence of problem modifications on given microprogrammed controllers · DAC 1980 |
Integrated circuit design › digital circuit design
logic design |
0.0 | 1 | 1980 | Optimization of the influence of problem modifications on given microprogrammed controllers · DAC 1980 |
Methods — techniques the papers use, named apart from their topics
bottom-up synthesis · 0.0synthesis algorithm · 0.0branch-and-bound · 0.0CAD · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2022 | Exact Polynomial Time Algorithm for the Response Time Analysis of Harmonic Tasks
Thi Huyen Chau Nguyen, Werner Grass, Klaus Jansen |
IWOCA | 2 |
| 2018 | Improved response-time bounds in fixed priority scheduling with arbitrary deadlines
Werner Grass, Thi Huyen Chau Nguyen |
Real Time Syst. | 1 |
| 2018 | Erratum to: Improved response-time bounds in fixed priority scheduling with arbitrary deadlines
Werner Grass, Thi Huyen Chau Nguyen |
Real Time Syst. | 1 |
| 2008 | Selected papers of the ARCS06 conference: an introduction
Werner Grass, Bernhard Sick, Theo Ungerer, Klaus Waldschmidt |
Pers. Ubiquitous Comput. | 1 |
| 2007 | Editorial
Klaus Waldschmidt, Jan Haase 0001, Werner Grass, Bernhard Sick |
J. Syst. Archit. | 3 |
| 2002 | Improved Constraints for Multiprocessor System SchedulingabstractMILP-based models are useful for finding optimal schedules and for proving their optimality. Because of the problem complexity, model improvements have to be investigated. We analyze the constraints necessary for precluding resource conflicts, present novel formulations, and evaluate them. The efficiency of the solution process can be improved significantly by selecting the proper formulation. Martin Grajcar, Werner Grass |
DATE | 2 |
| 1993 | Session A3: System specification I
Werner Grass |
Microprocess. Microprogramming | 1 |
| 1993 | Introducing structure into behavioural descriptions obtained from timing diagram specifications
Wolf-Dieter Tiedemann, Stefan Lenk 0001, C. Grobe, Werner Grass |
Microprocess. Microprogramming | 4 |
| 1990 | Global Hardware Synthesis from Behavioral Dataflow DescriptionsabstractThis paper reports on a new bottom-up synthesis technique for general behavioral descriptions. Our technique extends traditional straight-line code synthesis by allowing hierarchical, block-structured dataflow graphs with block-level parallelism. Program path probabilities are taken into account; and both high-level synthesis and design-space exploration are addressed. Josef Scheichenzuber, Werner Grass, Ulrich Lauther, Sabine März |
DAC | 2 |
| 1987 | BOSS - A functional - Block oriented intermediate language for RT - Level hardware descriptions
Werner Grass, Rainer Buschke, Reinhard Rauscher |
Microprocessing and Microprogramming | 1 |
| 1985 | Some results on the design of regular structured sequential circuits
Werner Grass |
Integr. | 1 |
| 1983 | A synthesis system for PLA-based programmable hardware
Werner Grass |
Microprocessing and Microprogramming | 1 |
| 1982 | A depth-first branch-and-bound algorithm for optimal PLA foldingabstractIn this paper we are concerned with the PLA folding problem defined by Hachtel, Newton and Sangiovanni-Vincentelli. We propose a depth first branch and bound procedure for optimizing simultaneous row and column folding. With our procedure one can compute such a PLA folding which is optimal with respect to different practical constraints. We present some results of an implemented algorithm that is restricted to row folding. Werner Grass |
DAC | 1 |
| 1980 | Optimization of the influence of problem modifications on given microprogrammed controllersabstractFor the logic design of digital controllers, efficient synthesis algorithms have been published. Most of these assume, that a completely new hardware consisting of the fewest number of components has to be built. The implementation of those algorithms form an important part of a CAD system for logic design. In order to be accepted in practice, a CAD system has to take into account additional requirements. One of these concerns with the minimization of hardware changes caused by subsequent modifications of the control task which often become necessary after the completion of the hardware implementation. This paper describes a method which solves this problem for an universal structure of microprogrammed controllers. This method is implemented as a module of the CAD program system LOGE. LOGE supports the logic design of hardwired, microprogrammed, and microprocessor based controllers. LOGE already proved to be a powerful design tool in several industrial applications. Günter Biehl, Werner Grass, P. S. Hall |
DAC | 2 |