Almost all SoC designs today use hardware prototyping at some point of the development cycle to perform hardware/software validation or test interfaces to real-world stimulus. Recently, virtual prototypes have emerged as a way to run system level tests and perform hardware/software co-simulation before silicon or hardware prototypes are available. Does the emergence of virtual prototyping mean the end for FPGA-based prototypes? Will the hardware prototype continue to live on as an integral part of the SoC design cycle? Will hybrids of virtual and hardware prototypes be the answer? Join our expert panelists in a spirited discussion on the best approach for speeding the verification and validation of complex SoC using system prototypes. Virtual, hardware or hybrid -- which will reign supreme?

A crisis is a terrible thing to waste. Quotes like this are often heard by experts in the industry and academia but what does this mean to me? How should I change my professional interests? How should I evolve my career? How is EDA going to evolve? The panel represents multiple points of views on these questions. Four experts will review the current job situation in EDA and provide a historical perspective for previous recessions. The panel will further discuss views on new directions for the Electronics market, how EDA should evolve, and options for career development during the slow down of the industry.

This panel discusses power optimization at the system level. What are the needs and opportunities? What are examples of successful practices? Can system-level power optimizations ever be automated? Can power optimizations be the enabling event for a methodology change in system-level design?

Multi Processor SoC (MPSoC) are being designed today. MPSoC design can help achieve aggressive performance and low power targets but it creates new design challenges: How to design the interconnect fabric and memory sub-system to allow the massive data movement required in a multi processor SoC environment? How to develop, debug and verify HW and SW functionality in a MPSoC design? Is MPSoC design an inflection point that will require new design methods including ESL methodologies?

Faced with continually coping with Moore's Law, computer-aided design (CAD) for integrated circuits is used to facing challenges in our ever-evolving design problem. Increasing device complexity is a perennial challenge and has led to several discontinuities in design methodology. Over the last decade deep submicron physical effects have significantly complicated the design process and required new efforts in design for manufacturability. With the emergence of multicore and manycore microprocessor systems we face a new type of challenge: Not only will our design object (the microprocessor systems themselves) take another leap in complexity, but for the first time in our industry's history we will need to fundamentally change the way we design and implement our software solutions as well. In this panel a broad set of representatives at the front lines of addressing this challenge will outline how they plan to respond. Representative questions to the panelists include:

Moving up in the level of abstraction is the holy grail of EDA. Each transition to the next level of abstraction allows 100x improvement in simulation speed and 100x improvement in design productivity. ESL is being promoted as the next level above RTL but is it really happening?