A clock suppression based technique that takes advantage of the higher abstraction level provided by synchronous design techniques to improve logic simulation performance was given by the authors (see Proc. IEEE Int. Conf. on Comput. Aided Des. Integr. Circuit Syst., pp.62-65, 1990). Here, the authors elaborate on those techniques and present extensions that can offer an average performance increase of over 5* and a peak performance increase of over 10* that of a conventional logic simulator. The viability of the approach is shown by presenting results from switch-level simulations of large industrial examples. It is shown that because clock suppression based techniques are CPU-bound, they can take advantage of the recent explosive growth of CPU performance.>

An overwhelming majority of logic designers use synchronous logic design techniques to manage the complexity of their designs and rely on logic simulation techniques for design verification. Yet, logic simulators do not take advantage of the higher abstraction level provided by synchronous logic design techniques to improve their performance. A general technique is presented which takes advantage of the high degree of periodicity common in synchronous logic designs. It is shown that a performance improvement of at least 200% occurs when these techniques are applied within the COSMOS. simulation system to simulate large digital systems.>

A methodology is presented for fault simulation of a system level diagnostic program involving large models (50000 to 200000 gates) and long test sequences. The accuracy of memory models and the interplay of fault insertion and fault selection with diagnostic program development are topics covered. It also details observation and statistical methods and tools used to investigate the operation of 'faulty machines' (the fault effects created by an individual fault source). Observation of individual faulty machines is critical to provide information about looping and erratic programs, violations to subprogram sequencing, etc. This methodology is a successful attempt to make fault simulation of system diagnostics feasible.>

A methodology is presented for fault-simulation of system level diagnostic programs involving large models (50000 to 200000 gates) and long test sequences. Accuracy of memory models, interplay of target faults with diagnostic program development, and creation of shorter diagnostics are topics covered. Observation and statistical methods and tools used to investigate the operation of the faulty machine within the diagnostic program are also presented. Observation of individual faulty machines is critical to provide information about looping and erratic programs, violations of subprogram sequencing, etc. This methodology makes fault simulation of system diagnostics feasible.>

A general-purpose traversal mechanism is described which is used to perform concurrent simulation for complex devices. This traversal mechanism performs all list handling necessary for an accurate and efficient concurrent simulation at a complexity level much higher than that of the gate level. The work on this general-purpose traversal mechanism project has been done within the DECSIM logic simulator. The work to date includes the realization of concurrent MOS fault simulation and the early stage of designing concurrent behavior fault simulation.>

Fault simulation of circuits described at multiple levels of abstraction (RT, gate, switch) is a major problem in the area of CAD and testing. Although the concurrent paradigm is generally acknowledged as the most efficient, several techniques are crucial to successfully extend it to multilevel simulation of large circuits. In particular, based on multilist traversal, fraternal event processing, list events, and levelizing, advances are presented here in simulation speed, accuracy, and generality. For zero-delay elements, the simulation of irrelevant activity is avoided, but the accuracy of structural (interconnect) logic simulation is maintained. What is described here has been implemented in MOZART, and detailed experimental results are reported. Relative to the good machine, the average faulty machine is simulated 900 to 17 000 times faster. The approach presented is not restricted to fault simulation, and is thus applicable to the new area of concurrent case simulation.

A well-known fundamental computer technique consists of the “interpretation” of naturally available or artifically formed data items as addresses to perform table-lookups. Although well-known, this technique is still not exploited to its fullest potential. The power and extent of this technique as applied to logic simulation is demonstrated.

Basic goals for logic and fault simulation are accuracy, execution speed, and modeling ease. Accuracy means that adequate state and timing detail must be maintained, and that good and faulted networks must be simulated with equal accuracy. High speed simulation is desirable to perform massive fault simulations of large networks, and modeling ease is desirable to build models easily and quickly.