Demo Data from EDBT 2026 / reviewers in the wild / expert
David Cyrluk
dblp:91/5716
· DBLP profile ↗
8ranked-venue papers
7as first author
0since 2021 · last 1997
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Theory of computation · 5 · 5 first-authorSoftware engineering, systems software and programming languages · 4 · 4 first-authorArtificial intelligence and machine learning · 3 · 2 first-authorSystems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Theoretical computer science
2 papers |
Automated reasoning and model checking · 91% Logic in computer science · 9% | |
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% | |
| Artificial intelligence
1 paper |
3D vision · 100% | |
| Computer graphics and multimedia
1 paper |
Geometric modeling and processing · 100% |
Topics — the 5 heaviest of 6, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Automated reasoning and model checking › decision procedures
bit-vector reasoning |
0.0 | 1 | 1997 | An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors · CAV 1997 |
Automated reasoning and model checking
decision procedures |
0.0 | 1 | 1997 | An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors · CAV 1997 |
Electronic design automation › hardware verification and test
hardware verification |
0.0 | 1 | 1994 | Ground Temporal Logic: A Logic for Hardware Verification · CAV 1994 |
Computer vision › 3D vision
geometric reasoning |
0.0 | 1 | 1988 | A Multi-Level Geometric Reasoning System for Vision · Artif. Intell. 1988 |
Logic in computer science
temporal logic |
0.0 | 1 | 1994 | Ground Temporal Logic: A Logic for Hardware Verification · CAV 1994 |
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1997 | An Efficient Decision Procedure for the Theory of Fixed-Sized Bit-Vectors
David Cyrluk, M. Oliver Möller, Harald Ruess |
CAV | 1 |
| 1997 | Systematic Formal Verification of InterpretersabstractFormal methods have gained acceptance in the hardware field through a pragmatic approach that has succeeded in providing systematic, scalable, highly automated, and cost effective treatments for certain stereotypical problems of practical importance. By identifying stereotypical problems, the effort required to develop effective formal methods has been amortized over many applications. We suggest that formal methods can achieve similar industrial success in selected software applications by following the same principles. As an illustration, we examine approaches to the stereotypical problem of interpreter correctness in the presence of timing differences between the specification and implementation interpreters. In hardware, this corresponds to the problem of verifying microprogrammed, pipelined, or superscalar processors, but it has wider applications to any system-hardware or software-that can be considered as an interpreter. David Cyrluk, John M. Rushby, Mandayam K. Srivas |
ICFEM | 1 |
| 1996 | On Shostak's Decision Procedure for Combinations of Theories
David Cyrluk, Patrick Lincoln, Natarajan Shankar |
CADE | 1 |
| 1996 | Inverting the Abstraction Mapping: A Methodology for Hardware Verification
David Cyrluk |
FMCAD | 1 |
| 1995 | Theorem proving: not an esoteric diversion, but the unifying framework for industrial verificationabstractThe effectiveness of hardware verification techniques has increased markedly in the past decade. As hardware verification techniques become increasingly powerful the idea of transitioning verification technology to industry can be taken seriously. Nevertheless, powerful decision procedures that can completely automate the verification of certain types of hardware, whether they are BDD based model-checkers or automatic microprocessor verification tools, cannot be adequate on their own for industrial hardware verification. However, a high-level, general-purpose theorem prover with specific capabilities can provide an overall framework in which these tools can be embedded and in which they can then be effectively used for industrial hardware verification. David Cyrluk, Mandayam K. Srivas |
ICCD | 1 |
| 1994 | Ground Temporal Logic: A Logic for Hardware Verification
David Cyrluk, Paliath Narendran |
CAV | 1 |
| 1988 | GEOMETER: A Theorem Prover for Algebraic Geometry
David Cyrluk, Richard M. Harris, Deepak Kapur |
CADE | 1 |
| 1988 | A Multi-Level Geometric Reasoning System for Vision
Michele Barry, David Cyrluk, Deepak Kapur, Joseph L. Mundy, Van-Duc Nguyen |
Artif. Intell. | 2 |