Real Time performance testing can be divided into two distinct parts: system test and algorithm test. System test checks that the right functions operate on the right data within power, latency, and other constraints under all conditions. Major RAN OEMs, put as much effort into system test and debug as they do into algorithm test, to ensure a competitive product. An algorithm tester will provide little insight into real time and hardware-software (HW-SW) capacity as it is unaware of the system implementation. In this paper we present an innovative Digital Twin technology, which we call Declarative Digital Twin (DDT). A DDT can describe the system requirements of the RAN such that critical corner cases can be found via automation, that would normally be missed by conventional testing. This is possible even when the RAN requirements are only partially specified. We present a Domain Specific Language (DSL) for declarative description of the RAN and show results from an automated solver that demonstrate how potential HW-SW implementation related corner cases can be identified from the DDT of an ORAN DU.

Over the last decade the relative latency of access to shared memory by multicore increased as wire resistance dominated latency and low wire density layout pushed multi-port memories farther away from their ports. Various techniques were deployed to improve average memory access latencies, such as speculative pre-fetching and branch-prediction, often leading to high variance in execution time which is unacceptable in real-time systems. Smart DMAs can be used to directly copy data into a layer-1 SRAM, but with overhead. The VLIW architecture, the de-facto signal-processing engine, suffers badly from a breakdown in lock-step execution of scalar and vector instructions. We describe the Split Latency Adaptive Pipeline (SLAP) VLIW architecture, a cache performance improvement technology that requires zero change to object code, while removing smart DMAs and their overhead. SLAP builds on the Decoupled Access and Execute concept by 1) breaking lock-step execution of functional units, 2) enabling variable vector length for variable data-level parallelism, and 3) adding a novel triangular-load mechanism. We discuss the SLAP architecture and demonstrate the performance benefits on real traces from a wireless baseband-system (where even the most compute intensive functions suffer from an Amdahl’s law limitation due to a mixture of scalar and vector processing).

Manycore SoC architectures based on on-chip shared memory are preferred for flexible and programmable solutions in many application domains. However, the development of many ported memory is becoming increasingly challenging as we approach the end of Moores Law while systems requirements demand larger shared memory and more access ports. Memory can no longer be designed simply to minimize single transaction access time, but must take into account the functionality on the SoC. In this paper we examine a common large memory usage in SoC, where the memory is used as storage for large buffers that are then moved for time scheduled processing. We merge two aspects of many ported memory design, combinatorial analysis of interconnect, and geometric analysis of critical paths, extending both to show that in this case the SoC performance benefits significantly from a hierarchical, distributed and staged architecture with lower-radix switches and fractal randomization of memory bank addressing, along with judicious and geometry aware application of speed up. The results presented show the new architecture supports 20% higher throughput with 20% lower latency and 30% less interconnection area at approximately the same power consumption. We demonstrate the flexibility and scalability of this architecture on silicon from a physical design perspective by taking the design through layout. The architecture enables a much easier implementation flow that works well with physically irregular port access and memory dominant layout, which is a common issue in real designs.

For low-resolution analog-to-digital converter (ADC) systems, only high-complexity receive antenna selection has been developed and transmit antenna selection has been limited to a single antenna selection in prior work. In this paper, we propose low-complexity receive antenna selection algorithms and analyze transmit antenna selection by considering antenna selection at a base station with large antenna arrays and low-resolution ADCs. For downlink antenna selection, we show a selection criterion with zero-forcing precoding equivalent to a perfect quantization system; sum rate increases with number of selected antennas; derivation of the sum rate loss function from using a antenna subset; and sum rate loss reaches a maximum at a point of total transmit power and decreases beyond that point to converge to zero. For wideband orthogonal-frequency-division-multiplexing (OFDM) systems, our results hold when entire subcarriers share a common subset of antennas. For uplink antenna selection, we generalize a greedy antenna selection criterion; propose a quantization-aware fast antenna selection algorithm using the criterion; and derive a lower bound on sum rate achieved by the proposed algorithm. For wideband OFDM systems, we extend our algorithm and derive a lower bound on its sum rate. Simulation results validate theoretical analyses and show increases in sum rate over conventional algorithms.

In this paper, we investigate learning-based maximum likelihood (ML) detection for uplink massive multiple-input and multiple-output (MIMO) systems with one-bit analog- to-digital converters (ADCs). To overcome the significant dependency of learning-based detection on the training length, we propose two one-bit ML detection methods: a biased-learning method and a dithering-and-learning method. The biased-learning method keeps likelihood functions with zero probability from wiping out the obtained information through learning, thereby providing more robust detection performance. Extending the biased method to a system with knowledge of the received signal-to-noise ratio, the dithering-and- learning method estimates more likelihood functions by adding dithering noise to the quantizer input. The proposed methods are further improved by adopting the post likelihood function update, which exploits correctly decoded data symbols as training pilot symbols. The proposed methods avoid the need for channel estimation. Simulation results validate the detection performance of the proposed methods in symbol error rate.

One way to reduce the power consumption in large-scale multiple-input multiple-output (MIMO) systems is to employ low-resolution analog-to-digital converters (ADCs). In this paper, we investigate antenna selection for large-scale MIMO receivers with low-resolution ADCs, thereby providing more flexibility in resolution and number of ADCs. To incorporate quantization effects, we generalize an existing objective function for a greedy capacity-maximization antenna selection approach. The derived objective function offers an opportunity to select an antenna with the best tradeoff between the additional channel gain and increase in quantization error. Using the generalized objective function, we propose an antenna selection algorithm based on a conventional antenna selection algorithm without an increase in overall complexity. Simulation results show that the proposed algorithm outperforms the conventional algorithm in achievable capacity for the same number of antennas.

Heterogeneous computing platforms with multiple types of computing resources have been widely used in many industrial systems to process dataflow tasks with pre-defined affinity of tasks to subgroups of resources. For many dataflow workloads with soft real-time requirements, guaranteeing fast and bounded response times is often the objective. This paper presents a new set of analysis techniques showing that a classical real-time scheduler, namely earliest-deadline first (EDF), is able to support dataflow tasks scheduled on such heterogeneous platforms with provably bounded response times while incurring no resource capacity loss, thus proving EDF to be an optimal solution for this scheduling problem. Experiments using synthetic workloads with widely varied parameters also demonstrate that the magnitude of the response time bounds yielded under the proposed analysis is reasonably small under all scenarios. Compared to the state-of-the-art soft real-time analysis techniques, our test yields a 68% reduction on response time bounds on average. This work demonstrates the potential of applying EDF into practical industrial systems containing dataflow-based workloads that desire guaranteed bounded response times.

A spectrum- and energy-efficient system is essential for millimeter wave communication systems that require large antenna arrays with power-demanding ADCs. We propose an ADC bit allocation (BA) algorithm that solves a minimum mean squared quantization error problem under a power constraint. Unlike existing BA methods that only consider an ADC power constraint, the proposed algorithm regards total receiver power constraint for a hybrid analog-digital beamforming architecture. The major challenge is the non-linearities in the minimization problem. To address this issue, we first convert the problem into a convex optimization problem through real number relaxation and substitution of ADC resolution switching power with constant average switching power. Then, we derive a closed-form solution by fixing the number of activated radio frequency (RF) chains M. Leveraging the solution, the binary search finds the optimal M and its corresponding optimal solution. We also provide an off-line training and modeling approach to estimate the average switching power. Simulation results validate the spectral and energy efficiency of the proposed algorithm. In particular, existing state-of-the-art digital beamformers can be used in the system in conjunction with the BA algorithm as it makes the quantization error negligible in the low-resolution regime.

Owing to its reduction in hardware complexity and power consumption, hybrid beam-forming has become one of the most promising substitutes for fully digital beam-forming (FDB) in large antenna array systems. In conventional hybrid beam-forming (CHB) architecture, phase shifters are designed to operate at RF band and inaccuracies of the RF phase shifts are unavoidable in practice. Furthermore, these RF phase shifters still consume considerable power if implemented as active devices or a large space/area on dice (form factor) if implemented as passive devices. This issue becomes more critical for massive MIMO systems where lower power consumption and smaller form factor are much desired due to the large number of antenna elements. Aiming at reducing power consumption and form factor of the receiver, we investigate a new method to insert phase shifts via adjusting sampling-offset on sample and hold (S&H) circuit. Based on this method, a new receiver architecture with RF under-sampling technique and adjustable S&H circuit is proposed. We also develop a method to find out the required phase shifts for the beam-forming in the proposed receiver architecture. Performance evaluation at 28 GHz band shows that the proposed technology gives practically the same bit error rate (BER) performance as the CHB architecture but yields advantages in terms of power consumption, chip area, and beam-forming phase errors, which makes it appealing for massive MIMO systems.

Millimeter wave (mmWave) systems operating over a wide bandwidth and using a large number of antennas impose a heavy burden on power consumption. In a massive multiple-input multiple-output (MIMO) uplink, analog-to-digital converters (ADCs) would be the primary consumer of power in the base station receiver. This paper proposes a bit allocation (BA) method for mmWave multi-user (MU) massive MIMO systems under a power constraint. We apply ADCs to the outputs of an analog phased array for beamspace projection to exploit mmWave channel sparsity. We relax a mean square quantization error (MSQE) minimization problem and map the closed-form solution to non-negative integer bits at each ADC. In link-level simulations, the proposed method gives better communication performance than conventional low-resolution ADCs for the same or less power. Our contribution is a near optimal low-complexity BA method that minimizes total MSQE under a power constraint.

In this paper, we propose space-time fronthaul compression of baseband uplink LTE signals for cellular networks, in which baseband units (BBUs) support remote radio heads (RRHs) through fronthaul links. In particular, we assume massive antenna arrays in which the number of antennas in a RRH is much larger than the number of active users. The proposed method consists of two phases: dimensionality reduction phase and individual quantization phase. The key idea of the first phase is to apply principal component analysis (PCA). It performs low-rank approximation of a matrix - composed of received signals - by exploiting the correlation of the received signals across space and time. In the second phase, our method individually quantizes the dimensionality-reduced signal by applying transform coding with bit allocation to reduce the number of quantization bits. An LTE link-level simulator provides numerical results which show that the method achieves up to 8 × compression ratio for the uplink with 64 antennas and 4 active users, along with improvement in communication system performance as a result of denoising.

In a two tier cellular network comprised of a central macrocell underlaid with shorter range femtocell hotspots cross-tier interference limits overall capacity with universal frequency reuse. To quantify near-far effects, this paper derives a fundamental relation providing the largest feasible cellular signal-to-interference plus noise ratio (SINR), given any set of feasible femtocell SINRs. A distributed utility-based SINR adaptation at femtocells is proposed in order to alleviate cross-tier interference at the macrocell. The Foschini-Miljanic (FM) algorithm is a special case of the adaptation. Each femtocell maximizes their individual utility consisting of a SINR based reward less an incurred cost (cross-tier interference). Results show greater than 30% improvement in mean femtocell SINRs relative to FM. An algorithm is proposed that adaptively curtails transmission powers of the strongest femtocell interferers. Simulations show that a cell-edge user can achieve its SINR target even with 100 femtocells/cell-site (with typical cellular parameters).

In this paper we discuss our initial experiences adapting OpenMP to enable it to serve as a programming model for high performance embedded systems. A high-level programming model such as OpenMP has the potential to increase programmer productivity, reducing the design/development costs and time to market for such systems. However, OpenMP needs to be extended if it is to meet the needs of embedded application developers, who require the ability to express multiple levels of parallelism, real-time and resource constraints, and to provide additional information in support of optimization. It must also be capable of supporting the mapping of different software tasks, or components, to the devices configured in a given architecture.

In a two tier cellular network - comprised of a central macrocell underlaid with shorter range femtocell hotspots - cross-tier interference limits overall capacity with universal frequency reuse. To quantify near-far effects with universal frequency reuse, this paper derives a fundamental relation providing the largest feasible cellular Signal-to-Interference-Plus-Noise Ratio (SINR), given any set of feasible femtocell SINRs. We provide a link budget analysis which enables simple and accurate performance insights in a two-tier network. A distributed utility- based SINR adaptation at femtocells is proposed in order to alleviate cross-tier interference at the macrocell from cochannel femtocells. The Foschini-Miljanic (FM) algorithm is a special case of the adaptation. Each femtocell maximizes their individual utility consisting of a SINR based reward less an incurred cost (interference to the macrocell). Numerical results show greater than 30% improvement in mean femtocell SINRs relative to FM. In the event that cross-tier interference prevents a cellular user from obtaining its SINR target, an algorithm is proposed that reduces transmission powers of the strongest femtocell interferers. The algorithm ensures that a cellular user achieves its SINR target even with 100 femtocells/cell-site (with typical cellular parameters) and requires a worst case SINR reduction of only 16% at femtocells. These results motivate design of power control schemes requiring minimal network overhead in two-tier networks with shared spectrum.

We develop a new construction criterion for BSPK space-time codes. Based on this criterion, we propose a new method of improving the performance of space-time codes, namely bit interleaving. Then, we provide a computationally effective, iterative way of decoding bit interleaved space-time codes. At the end, we note the 2 dB gain due to the new approach. A proposed 16 state bit interleaved code operates close to 3 dB from the outage probability.

Gaussian frequency shift keying modulation has been chosen as the modulation technique for the physical layer of Bluetooth. Bluetooth is a standard for low cost and low power wireless communications between various mobile devices. The optimal demodulation of a GFSK signal involves an extremely complex Viterbi decoder. Therefore designers have opted for the noncoherent detection of GFSK which uses a frequency discriminator, followed by symbol by symbol detection. We describe a decision feedback equalizer to be added after the discriminator. The DFE receiver gives gains in excess of 2 dB. We also describe how to increase the current data rate of a Bluetooth system by increasing the symbol rate and not the alphabet size.

Starting with an ordinary parallel concatenated turbo encoder in a block fading Rayleigh channel, we introduce bit-interleaving of the outputs, not for time diversity, but to increase the coding gain. We develop a guideline metric for designing QPSK space-time codes which reveals both the coding and diversity advantage of the systems as well as showing that it is unnecessary to guarantee full space diversity to achieve good performance in Rayleigh fading. Using channel a priori information in the MAP iterations for decoding, we achieve frame error rates within 1 dB of the outage probability with only modest increases in decoding complexity.

We describe a technique to control the trade-off between the error floor and the waterfall performance of parallel concatenated trellis-coded. modulation (PCTCM), which is also known as turbo TCM, via the choice of coded-bits-to-signal mapping for a fixed component code. We demonstrate that different choice of mapping leads to different error floor and waterfall performance. One mapping may have the lowest error floor but result in poor waterfall performance, while another mapping may achieve the opposite. We then present the time-varying mixed mapping scheme for PCTCM systems. The proposed mixed mapping scheme enables us to generate a set of turbo trellis codes from two choices of coded-bits-to-signal mapping with various waterfall performance and error floor.

In this paper, a bit-error-rate (BER) analysis for closed-loop transmit diversity in a time-selective Rayleigh fading channel containing feedback delay is presented. In the absence of feedback delay, closed-loop transmit diversity always outperforms open-loop transmit for a given transmitted signal energy. This is no longer true in the presence of feedback delay. We derive closed-form expressions of the average BER for this case assuming QPSK and BPSK signaling. The results of the analysis are instrumental for comparing closed-loop with open-loop schemes under given operating conditions. In particular, we demonstrate that, for a given transmitted energy and number of transmit antennas, open-loop outperforms closed-loop at sufficiently fast channel fading. We also show that, for a given transmitted signal energy and fading rate, closed-loop outperforms open-loop for sufficiently large numbers of transmit antennas while the total average transmitted signal energy is kept constant. For some special cases, closed-form expressions for the fading rate at which the performance of open-loop is equal to closed-loop are obtained.

This paper discusses the design tradeoffs and implementation options for building wideband CDMA systems. System on a chip (SOC) solutions have a range of implementation options, from processor cores to custom ASIC (or a mix of both), to satisfy the extremely challenging requirements of the digital baseband of a next generation wireless system. Additionally, good designs should have a roadmap that will take advantage of rapid improvements in process technology. This paper describes the use of coprocessors alongside DSPs to meet the demanding computational requirements of WCDMA. We show that a coprocessor based design still achieves reasonably efficient area and power use, maintains a high degree of programmability and has a good technology migration path.

This document describes two methods for reducing computational requirements during idle transmission in remote access systems incorporating digital subscriber line (DSL) modems, including asymmetrical DSL (ADSL) systems. These methods save processing power during idle transmission by generating an idle signal using low-complexity techniques. The generated idle signal is made spectrally compatible with xDSL systems and a nondisruptive signaling scheme is used to indicate to the far-end receiver the transition between idle to active or active to idle status. A technique is presented that modulates the phase of the pilot tone to signal status transitions to the remote receiver. The computational complexity at the receiver is reduced because full demodulation and decoding is not required to determine that an idle signal is being transmitted.

This paper describes a new variant of the least-mean-squares (LMS) algorithm, with low computational complexity, for updating an adaptive filter. The reduction in complexity is obtained by using values of the input data and the output error, quantized to the nearest power of two, to compute the gradient. This eliminates the need for multipliers or shifters in the algorithm's update section. The quantization itself is efficiently realizable in hardware. The filtering section is unchanged. Thus, this algorithm is similar to the sign based variants of the LMS algorithm. However, the complexity of the proposed algorithm is lower than that of the sign-error LMS algorithm, while its performance is superior to this algorithm. In particular, it is close to that of the regular LMS algorithm. The new algorithm also requires much lower area for ASIC implementation.

In discrete multitone (DMT) a time domain equalizer is used to shorten the length of the channel to less than the length of the cyclic prefix. The weights of this equalizer are set during initialization using a training sequence. Current techniques that rely on a version of on-line frequency domain LMS show low and uncertain convergence. Here, we show that off-line techniques that estimate the channel first, have much lower complexity, while providing much better performance. We describe a solution that requires a minimum eigenvalue to be found and show that this can be done with relatively low complexity. We also describe an off-line technique based on time domain LMS.

A parallelizable ADFE (adaptive decision feedback equalizer) is presented which performs at an error rate close to that of the serial DFE. The complexity of the parallel architecture grows linearly with the speedup, with the constant of growth being unity. This allows for parallelization of the DFE to a reasonable level without a prohibitive increase in complexity. The complexity of each section of the parallel DFE is on the order of s/sup 2/ where s is the number of taps in the serial DFE. For a serial DFE the complexity is of order s. Therefore, for a speedup of T, one requires a hardware complexity that is on the order sT times that of the serial DFE. The increase in complexity is therefore linear in both speedup and number of taps.>

A parallel adaptive decision feedback equalizer (ADFE) architecture is proposed. It allows adaptation at every sample to effectively equalize intersymbol interference for applications that operate at high sampling rates and require fast tracking capability. It is shown that if the effect of error propagation is small, the filter coefficients of the parallel ADFE will be exactly the same as those of a serially adapting ADFE. Simulation confirms that the parallel ADFE effectively tracks a time-varying channel with typical signal-to-noise ratios at a sampling rate four times higher than that of a serial ADFE, while under the same channel condition a previously proposed block ADFE fails to converge and becomes unstable.>