Demo Data from EDBT 2026 / reviewers in the wild / expert
P. J. H. Elias
dblp:91/6307
· DBLP profile ↗
1ranked-venue papers
1as first author
0since 2021 · last 1996
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1 · 1 first-author
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 100% |
Topics — the 4 heaviest of 4, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
circuit simulation and modeling |
0.0 | 1 | 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency · DAC 1996 |
Electronic design automation
interconnect modeling |
0.0 | 1 | 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency · DAC 1996 |
Electronic design automation
physical design |
0.0 | 1 | 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency · DAC 1996 |
Electronic design automation › circuit simulation › reduced-order modeling
RC network reduction |
0.0 | 1 | 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal Frequency · DAC 1996 |
Methods — techniques the papers use, named apart from their topics
scan-line approach · 0.0model order reduction · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 1996 | Extracting Circuit Models for Large RC Interconnections that are Accurate up to a Predefined Signal FrequencyabstractThis paper presents a technique that transforms large and complex RC networks into much smaller, physically realizable RC networks. These models reflect the transmission behavior of the initial network accurately for frequencies up to a user-defined maximal signal frequency. This technique has been incorporated in a layout-to-circuit extractor, using a scan-line approach. The method guarantees numerical stability and performs excellently in modeling RC interconnects. 1 Introduction This paper presents a solution to the major problem how to obtain a simple, passive and physically realizable RC network that matches the transmission behavior of a given very large and complex RC network up to a predefined maximal signal frequency. This problem is particularly acute in (3-D) layout-to-circuitextraction, where appropriate models for the IC interconnections in VLSI designs have to be generated. In most VLSI circuits, the IC interconnections and their parasitics play an essential role in th... P. J. H. Elias, N. P. van der Meijs |
DAC | 1 |