Processors with multiple functional units, including the superscalars, achieve significant performance enhancement through low-level execution concurrency. In such processors, multiple instructions are often issued and definitely executed concurrently and out-of-order. Consequently, interrupt and exception handling becomes a vexing problem. The authors identify latency, cost, and performance degradation as factors that must be considered in evaluating the effectiveness of interrupt and exception handling schemes. They then briefly enumerate proposals and implementations for interrupt and exception handling on out-of-order execution processors. An efficient hardware mechanism, the instruction window (IW), and an approach which allows for precise, responsive, and flexible interrupt and exception handling are presented. The implementation of the IW is discussed. The design of an eight-cell IW has been carried out; it can work with a very short machine cycle time. A comparison of all interrupt and exception handling schemes for out-of-order execution processors is also presented.>

The achievement of fast, precise interrupts and the implementation of multiple levels of branch predictions are two of the problems associated with the dynamic scheduling of instructions for superscalar processors. Their solution is especially difficult if short cycle time operation is desired. We present solutions to these problems through the development of the Fast Dispatch Stack (FDS) system. We show that the FDS is capable of scheduling storage, branch, and register-toregister instructions for concurrent and out-oforder executions; the FDS implements fast and precise interrupts in a natural, efficient way; and it facilitates speculative execution -- Instructions preceding and following one or more predicted conditional branch instructions may issue. When necessary, their effects are undone in one machine cycle. We evaluated the FDS system with extensive simulations.

Processors with multiple functional units, such as CRAY-1, Cyber 205, and FPS 164, have been used for high-end scientific computation tasks. Much effort has been put into increasing the throughput of such systems. One critical consideration in their design is the identification and implementation of a suitable instruction issuing scheme. Existing approaches do not issue enough instructions per machine cycle to fully utilize the functional units and realize the high-performance level achievable with these powerful execution resources.

This paper presents the design of a fast inner product processor, with appreciably reduced latency and cost The inner product processor is implemented with a tree of carry propagate or carry save adders; this tree is obtained with the incorporation of three innovations in the conventional multiply/add tree: (1) The leaf-multipliers are expanded into adder subtress, thus achieving an O(logNb) latency, where N denotes the number of elements in a vector and b the number of bits in each element (2) The partial products, to be summed in producing an inner product, are reordered according to their "minimum alignments", bringing approximately a 20% saving in hardware. (3) The reordering also truncates the carry propagation chain in the final propagation stage by 2 log b − 1 positions, significantly reducing the latency further. A form of the Baugh and Wooley algorithm is adopted to implement two's complement notation with changes only in peripheral hardware.

This paper studies one of the most difficult and important problems in the design of cost-effective multiple-microprocessor systems. The combined effect of interference due to bus contentions and that due to memory conflicts is investigated. Reference models are defined and applied to obtain analytic results which can prove to be valuable tools in the design of multiple-microprocessor systems for time-critical control processes. The effect of memory mapping is also investigated and an algorithm is developed to obtain a mapping which can be used to minimize memory conflicts.

This paper studies the problem of interconnecting circuit modules in microprocessor and digital system design. This problem is ever-present and has generally been handled in a heuristic manner.

A quantitative and systematic design procedure for multiple function-unit (MFU) processors and microprocessors is presented in this paper. The MFU organization employs a set of function units such as adders, multipliers, etc. to concurrently execute instructions from a single instruction stream. A set of parameters describing this processor organization and the programs it executes are presented. The instruction execution rate is used as the measure of performance. This can be defined as the number of instructions executed per unit time. An analytic model is presented which relates the performance of a processor to the parameters describing it. A general problem is formulated: ``Construct a processor that is optimal with respect to a certain design criterion.'' Two design criteria, which specify two design problems, are presented. The minimum cost (MC) problem specifies an optimal processor as one with a minimum cost while maintaining a minimal acceptable performance level. The maximum performance-to-cost ratio (MPCR) problem requires that the performance-to-cost ratio be maximized for the optimal processor. The design problem is formulated as an integer nonlinear programming problem. The branch and bound technique and other considerations are introduced to reduce the extent and amount of enumerations required. Illustrative examples are provided.

A 2-dimensional cellular general-purpose computer is specified. This particular cellular computer is distinguished from previously proposed, locally-controlled cellular computers in that the cellular structure is "hidden" from the user. At the ISP level, the machine is similar to a small-scale computer of the von Neumann type. However, the architecture of the computer does not feature physically isolated functional units to implement memory, processor, or control. As a result, we present a machine which may be programmed in the conventional manner, but which has the hardware advantages associated with the cellular structure. Additionally, the machine is controlled by a software microprogram, which lends itself to dynamic micro-programming and to such related applications as machine simulation.

Abstract—This paper treats the problem of finding efficient secondary assignments for synchronous sequential circuits. It presents a straightforward approach which identifies codes resulting in the least number of memory elements and sets of simple next-state functions, expressed in the sum-of-product form.

A distinct and straightforward method to test and realize linearly-separable switching functions is presented. This method makes use of a universal map which facilitates the generation of inequalities and the detection of contradictions. It also eliminates any preprocessing (such as positivizing and ordering) of a given function. The concept of composite level is first defined. A map is then developed, which is not restricted by the number of variables in the given function. A switching function can be easily mapped. A simple process is presented to generate inequalities by inspection. This process will either conclude that the given function is not linearly-separable or generate a set of composite levels and, consequently, a set of weights for the threshold switching device. Two illustrative examples are provided.