Jai-Hoon Chung

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5ranked-venue papers

3as first author

0since 2021 · last 1999

—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 3 first-authorComputer networks · 1Security and privacy · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems

1 paper

Integrated circuit design · 56% Reconfigurable computing and FPGAs · 44%

Topics — the 2 heaviest of 3, each with the papers that count most for it

Topic	Weight	Papers	Last	Evidence papers
Reconfigurable computing and FPGAs block cipher implementation	0.0	1	1999	Hardware Design and Performance Estimation of the 128-bit Block Cipher Crypton · CHES 1999
Integrated circuit design › digital circuit design cryptographic hardware	0.0	1	1999	Hardware Design and Performance Estimation of the 128-bit Block Cipher Crypton · CHES 1999

Year	Publication	Venue	Position
1999	Hardware Design and Performance Estimation of the 128-bit Block Cipher Crypton Eunjong Hong, Jai-Hoon Chung, Chae Hoon Lim	CHES	2
1997	A Hybrid Performance Management Scheme for OAM Function Supporting QoS Management in ATM Network abstract This paper proposes a new scheme for an ATM OAM performance management function, hybrid performance management scheme. The performance management OAM function monitors network performance using OAM cells and executes mechanisms to prevent traffic congestion with relation to traffic control functions. For this purpose, the proposed scheme enables the switching system to perform different performance monitoring mechanisms according to the OAM management boundary of end-to-end or segment definition and also makes it possible to provide the detail information in traffic control functions detail. Young-Il Kim, Jai-Hoon Chung, Chang Soo Lim, Jai-Young Lee, Sang-Bae Lee	ICC (1)	2
1994	A new deadlock prevention scheme for nonminimal adaptive wormhole routing Jai-Hoon Chung, Hyunsoo Yoon, Seung Ryoul Maeng	Microprocess. Microprogramming	1
1992	A systolic array exploiting the inherent parallelisms of artificial neural networks Jai-Hoon Chung, Hyunsoo Yoon, Seung Ryoul Maeng	Microprocess. Microprogramming	1
1991	A Systolic Array Exploiting the Inherent Parallelisms of Artificial Neural Networks Jai-Hoon Chung, Hyunsoo Yoon, Seung Ryoul Maeng	ICPP (1)	1