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Nick Soveiko

dblp:91/7842 · DBLP profile ↗
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1ranked-venue papers
1as first author
0since 2021 · last 2010
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 1 · 1 first-author

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Computer architecture, parallel and distributed computing, and storage systems
1 paper
Electronic design automation · 91% High-performance computing · 9%

Topics — the 3 heaviest of 4, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Electronic design automation
circuit simulation		 0.112010
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › circuit simulation
parallel circuit simulation		 0.112010
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010
Electronic design automation › circuit simulation
steady-state analysis		 0.112010
Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2010

Methods — techniques the papers use, named apart from their topics

parallel nonlinear solver · 0.1message passing interface · 0.1
YearPublicationVenuePosition
2010 Comparison Study of Performance of Parallel Steady State Solver on Different Computer Architectures
abstract
A parallel solver for steady state analysis of nonlinear circuits is presented. The solver uses the Message Passing Interface specification for communications and is suitable for steady state simulation of very large nonlinear circuits. Performance of the solver is investigated on symmetric multiprocessing, non-uniform memory access, and distributed memory computer systems. Impact of memory subsystem constraints on the solver efficiency is evaluated.
Nick Soveiko, Michel S. Nakhla, Ramachandra Achar
 IEEE Trans. Comput. Aided Des. Integr. Circuits Syst.1