Three-dimensional Networks-on-Chips (3D-NoCs) have emerged as an alternative to further enhance the performance, functionality, and packaging density of 2D-NoCs. However, the increasing complexity of NoC routers, the continuous miniaturization of silicon technology, the lower operating voltages, and the higher operating frequencies have made the NoC increasingly vulnerable to soft errors. In particular, transient faults occurring in the route computation unit (RCU) can provoke misrouting which may lead to severe effects such as deadlocks or packet loss, corrupting the operation of the entire chip. By combining a reliable fault detection circuit leveraging circuit-level double-sampling, with a cost-effective rerouting mechanism, we develop a full fault-tolerance solution that can efficiently detect and correct such fatal errors before the affected packets leave the router. To validate the proposed solution, we also introduce a novel method for simulation-based fault-injection based on the NoC's gate-level netlist. Experimental results obtained from a partially and vertically connected 3D-NoC indicate that our solution can provide a high level of reliability in the presence of errors, at the expense of an area and power overhead of 4.1% and 6.8% respectively.

This paper presents a new and highly efficient approach for the estimation by fault injection of the sensitivity to Single Event Upsets of circuits implemented in Xilinx SRAM-based FPGAs. The proposed approach prioritizes fault injection in specific configuration bits subsets defined according to their contents and the type of FPGA resources that they are configuring. The new approach also allows maximizing either the number of critical bits flipped during the injection or the estimation accuracy of the critical bits number. The results show that the new approach outperforms the traditional random fault injection with speed up factors up to two orders of magnitude.

In this paper, a comparison between two HDL-based fault-injection methods, FT-UNSHADES and NETFI, is presented. Fault-injection campaigns were performed on a third party example, named KECCAK sponge function family circuit dedicated for cryptography which is available as an open core. The comparison of both methodologies shows a similarity in the results and enlightens a problem that affects fault-injection systems related to how the synthesis and the simulation is made.

The current technological challenge for computing systems is to use multicore processors in order to ensure reliability, improve performance, and reduce power consumption. This paper presents a method and preliminary results of SEU fault-injection campaigns performed on multicore systems in asymmetric multi-processing mode. The target used for this purpose was a Quad-core processor. This work aims at validating the efficiency of TMR fault-tolerance method and to show the weakest variables of a given application running over multicore systems.

The goal of this work is to confront SER predictions done with MUSCA SEP3 to measures performed at high altitude (in commercial planes) by means a generic and flexible experimental testboard developed by TIMA. In this case the testboard was a memory architecture of 1 Gigabit made from SRAMs issued from two successive generations, 130 nm and 90 nm, respectively named models 1 and 2 in the following.

This paper presents principles and results of dynamic testing of an SRAM-based FPGA using time- resolved fault injection with a pulsed laser. The synchronization setup and experimental procedure are detailed. Fault injection results obtained with a DES crypto-core application implemented on a Xilinx Virtex II are discussed.

In this paper are first summarized representative examples of anomalies observed in systems operating on-board satellites as the consequence of the effects of radiation on integrated circuit, showing that single event upsets (SEU) are a major concern. An approach to predict the sensitivity to SEUs of a software application running on a processor-based architecture is then proposed. It is based on fault injection experiments allowing estimating the average rate of program dysfunctions per upset. This error rate, if combined with static cross-section figures obtained from radiation ground testing, provides an estimation of the target program error rate. The efficiency of this two-step approach was demonstrated by results obtained when applying it to various processors.

Benefits resulting from the adoption of SRAM-based FPGAs as design target technology in space applications are manifold. These devices, however, exhibit a potentially high susceptibility to single event upsets (SEU) due to the presence of a large number of configuration memory cells. As fault injection alone is not able to reach every circuitry inside FPGA, radiation ground testing is mandatory in order to perform the analysis on a larger set of SEU upsets. This paper presents a radiation test methodology for Xilinx Virtex FPGAs based on the THESIC+ system.

Obsolescence of electronic components is a big concern affecting most electronic equipments involved in safety critical applications (automotive, avionics, airframe, nuclear plants, military applications...). Indeed, such applications are active years longer than was originally anticipated. This paper addresses a methodology to validate emulated replacement solutions and propose solutions to be experienced on a Motorola 6800 processor to illustrate the proposed approach.

This paper deals with a software modification strategy allowing the on-line detection of transient errors. Being based on a set of rules for introducing redundancy in the high-level code, the method can be completely automated, and is particularly suited for low-cost safety-critical microprocessor-based applications. Experimental results from software and hardware fault injection campaigns are presented and discussed, demonstrating the effectiveness of the approach in terms of fault detection capabilities.

The authors present an evaluation of signature analysis efficiency which does not rely on assumptions about the distribution of the analyzed error sequences. This is achieved through the use of an 'a priori randomization' technique, which leads to a choice of LFSRs (linear feedback shift registers) corresponding to randomly chosen irreducible polynomials of a given degree. As it does not make use of assumptions on the error distribution, the proposed evaluation is more pessimistic than the usual ones. In particular, it takes into account the length of the analyzed sequence. However, it can be valuable when the efficiency of signature analysis has to be guaranteed, for highly dependable applications for instance.>

An effort has been made to evaluate the fault coverage of functional test methods. A study comparing a structural (manufacturing) test and three functional test methods, a tailored test, a systematic pseudo-exhaustive test, and a random test, is presented. The experiments were performed on defective microprocessors (6800 and 68000). Working with a nonbiased sample of circuits was a major concern; thus, randomly distributed defects were created on a set of good circuits by cutting either Al or poly-Si tracks using microcutter machine equipment. The results concerning defect coverage and Boolean defect coverage are largely better than those given by H.P. Klug (1988). The results indicate that the functional methods evaluated are very thorough. Random test seems to achieve an impressive fault coverage.>

A number of functional-level test approaches for microprocessors have been proposed. The GAPT approach, presented here, is a pragmatic one, but it is supported by a set of tools and experimental results. The authors describe the GAPT approach in detail. They draw tentative conclusions with respect to the effectiveness and scope of these functional test generation methods.>

This paper presents an automatic generation system for behavioral test programs of microprocessors. First, the test environment is presented, as well as its consequences on test program generation. In the second part, the test principles are outlined; it is a behavioral test, i.e a test determined from the user's description of the microprocessor; the resulting test programs are quite modular. The third part presents the description language and the generation system.