Emerging computing applications such as Artificial Intelligence (AI) are facing a memory wall with existing on-package memory solutions that are unable to meet the power-efficient bandwidth demands. We propose to enhance UCIe with memory semantics to deliver power-efficient bandwidth and cost-effective on-package memory solutions applicable across the entire computing continuum. We propose approaches by reusing existing LPDDR6 and HBM memory through a logic die that connects to the SoC using UCIe. We also propose an approach where the DRAM die natively supports UCIe instead of the LPDDR6 bus interface. Our approaches result in significantly higher bandwidth density (up to 10x), lower latency (up to 3x), lower power (up to 3x), and lower cost compared to existing HBM4 and LPDDR on-package memory solutions.

PCI Express®(PCIe®) specification has been doubling the data rate every generation in a backward compatible manner every three years. PCIe 6.0 specification will adopt PAM-4 signaling at 64.0 GT/s for maintaining the same channel reach, cost, and power profile as prior generations. A Forward Error Correction (FEC) mechanism will offset the high BER of PAM-4. A strong Cyclic Redundancy Check (CRC) and a link level replay mechanism will deliver a low-latency, high bandwidth efficiency, and highly reliable solution expected of a Load-Store interconnect. We propose a non-pipelined implementation of the FEC and CRC that is part of the PCIe 6.0 base specification. We also propose a partitionable and pipelined implementation for FEC and CRC for lowering gate count and latency. We have tested the correctness of our register transfer logic (RTL) implementation in a field programmable gate array (FPGA) implementation in addition to simulation. Synthesis results from the Synopsys DC compiler demonstrates that for a x16 PCIe Link partitionable to up to x4s, with 4 independent controllers using independently partitionable logic, we achieve a gate count of about 100,000 for the transmit and receive side with a FEC + CRC delay of less than 1 nano second (nsec) in each direction.

In this paper, we describe the design of Neurogrid, a neuromorphic system for simulating large-scale neural models in real time. Neuromorphic systems realize the function of biological neural systems by emulating their structure. Designers of such systems face three major design choices: 1) whether to emulate the four neural elements-axonal arbor, synapse, dendritic tree, and soma-with dedicated or shared electronic circuits; 2) whether to implement these electronic circuits in an analog or digital manner; and 3) whether to interconnect arrays of these silicon neurons with a mesh or a tree network. The choices we made were: 1) we emulated all neural elements except the soma with shared electronic circuits; this choice maximized the number of synaptic connections; 2) we realized all electronic circuits except those for axonal arbors in an analog manner; this choice maximized energy efficiency; and 3) we interconnected neural arrays in a tree network; this choice maximized throughput. These three choices made it possible to simulate a million neurons with billions of synaptic connections in real time-for the first time-using 16 Neurocores integrated on a board that consumes three watts.