This paper presents a 0.5V CMOS flipped gain buffer (FGB) which is realized in 40nm CMOS technology and dedicated to very low-power operation environment. The circuit is able to provide gain function whereas its parallel architecture enables it to perform rail-to-rail operation. The employment of feedback mechanism effectively allows it to drive resistive load. The simulation results have shown that at buffer input transistor’s gm of 1µA/V and bias current of 36.54nA, the circuit can drive a minimum load of 7.74kΩ//20pF whilst offering input common-mode range of (3mV-482mV), output common-mode range of (4mV-478mV) and 10dB gain. The achieved bandwidth is 224.06kHz. The proposed buffer has demonstrated with improved performance metrics with respect to that of source follower and flipped source follower. Therefore, it is very useful for very low-voltage analog signal processing applications.

This paper presents a digital current sensor for digitally-controlled current-ripple-based DC-DC buck converters to estimate the instantaneous inductor-current ripple accurately in both the Discontinuous (DCM) and Continuous (CCM) Current Modes. The current sensor employs a proposed dual-mode input multiplexing technique to select an appropriate representation of the pertinent voltage of the switching node$(\boldsymbol{V}_{\boldsymbol{x}})$in any mode, thereby allowing the current to be estimated more accurately compared to that of the prior-art design. The accurate inductor-current ripple information enables the controller to yield output-voltage transient response with small overshoot or undershoot (OS/US) and fast settling time. Benchmarking results using a digitally-controlled current-ripple constant on-time DC-DC buck converter show that the converter employing the proposed sensor achieves$\geq \mathbf{49}{\%}$smaller OS/US and$\geq \mathbf{45}{\%}$faster settling time at the output voltage in both the DCM and the CCM collectively compared with that of the same converter but with the prior-art sensor.

This paper presents an ultra-low supply 4-stage output-capacitorless low-dropout (LDO) regulator using a TSMC 40nm process. A novel frequency compensation scheme, which is called feedforward with embedded Miller-RC compensation (FEMRCC), is proposed to guarantee stability throughout the entire load range. The phase margin and gain margin are at least 45.4° and 6.5dB respectively. At a supply voltage of 0.6V, the regulator can support 0 to 150mA of load current. When the load current is stepped from 0 to 150mA, the regulator displays only a 1.5mV undershoot and 0.7mV overshoot, while consuming $39.3 \mu \mathrm{A}$ quiescent current. By utilizing a pseudo-differential cross-coupled pair as the input stage, the LDO regulator achieves a high unity gain bandwidth (UGB) of more than 24MHz. With four gain stages, the minimum DC gain is 55.2dB, ensuring excellent output regulation accuracy. The proposed design is suitable for Internet-of-Things applications with an excellent transient figure-of-merit (FoM) comparable to state-of-the-art designs.

In this article, an output-capacitorless low-dropout (OCL-LDO) regulator that features low-power, small-transient-spike, and process-temperature (PT)-aware design for transient sustainability is presented. The circuit architecture is based on the improved PT-aware current source for keeping stable bandwidth and the proposed PT-aware transistor biasing network in conjunction of dual fast local feedback (DFLF) loops in a single power transistor stage to yield both enhanced and sustained transient metrics under a sub-1-V supply. Fabricated in 40-nm CMOS technology, the regulator can deliver a full-load current of 100 mA at a 100-pF load under a 0.75-V supply. From the measured results of 12 samples, it consumes an average quiescent power of 19.5 μW and quiescent current of 26 μA. It displays an average settling time of 414 ns for a full-load current of 100 mA at room temperature. The average load transient voltage spike is 23.9 mV and small when compared to the reported works at a similar level of load current. Finally, the process corner simulations at different temperatures together with the 12 measured samples at temperature corners have validated the sustainability of transient metrics.

An ultralow quiescent current output-capacitorless low-dropout (LDO) regulator dedicated to Internet-of-Things applications is presented. This is based on an improved adaptive-stage adaptively biased architecture together with the novel frequency compensation to achieve the good stability and fast transient response under ultralow bias current. Validated by the CMOS 0.18-μm technology, the chip area is 0.055 mm2. The proposed LDO regulator consumes only 407-nA quiescent current at no-load current while providing a 1-V output with a maximum load current of 100 mA from a 1.2-V power supply. The adaptive frequency compensation is presented, including a new transistor degeneration frequency compensation (TDFC) to sustain the stability at ultralow quiescent bias. Besides, it also includes Q-reduction and Miller-RC compensation schemes to ensure the stability for full load current range. In addition, a substantial improved transient response is obtained by the proposed distributed overshoot reduction circuit together with the TDFC scheme and the adaptively feed-forward biasing topology. The measured results have shown that the undershoot/overshoot voltage is 117 mV/35.33 mV and the output can settle in 1.56 μs with 1% accuracy. Compared to fixed-biased and adaptively biased architectures, it shows the lowest value in figure of merit (FOM) at the quiescent state. Compared to adaptively biased architectures, it shows the improved FOM at the maximum quiescent state.

A novel relaxation oscillator (ROSC) with a merged window comparator, an optimized parallel/series composite resistor and a reference generator on the basis of threshold monitoring circuit is presented. The ROSC achieves offset cancellation by adopting the merged window comparator. The optimized composite resistor is employed to reduce the output frequency temperature coefficient (T.C.) even in the presence of process variation. The oscillator is realized in 65nm CMOS process. At a supply voltage of 1.2V, the current consumption is 7.47μA. The simulated frequency T.C. is 14.69ppm/°C over the temperature range of -20~120°C and the line sensitivity is 0.188%/V over the supply voltage range of 1.2~2.3V.

This paper presents a new nanometer-based low-power constant current reference that attains a small value in the total process-voltage-temperature variation. The circuit architecture is based on the embodiment of a process-tolerant bias current circuit and a scaled process-tracking bias voltage source for the dedicated temperature-compensated voltage-to-current conversion in a preregulator loop. Fabricated in a UMC 65-nm CMOS process, it consumes 7.18 μW with a 1.4 V supply. The measured results indicate that the current reference achieves an average temperature coefficient of 119 ppm/°C over 12 samples in a temperature range from -30 °C to 90 °C without any calibration. Besides, a low line sensitivity of 180 ppm/V is obtained. This paper offers a better sensitivity figure of merit with respect to the reported representative counterparts.

This paper presents a fully integrated process, supply voltage, and temperature compensated supply (PVTCS) for a point-of-load digital system. Through adding the appropriate weighted threshold voltage variation from the pMOS (ΔVTHP) and the nMOS (ΔVTHN) diodes to the reference voltage of a high-speed low-dropout voltage regulator, the supply of the digital circuit becomes adaptive, and hence, it minimizes the speed deviation in the context of PVT variations. Validated in a UMC 65-nm CMOS process, the simulation and the measurement results of an inverter chain-based oscillator have validated the effectiveness of PVTCS. It can significantly reduce the delay variations with respect to the uncompensated supply counterpart. The same goes for a sample critical path-based oscillator with extensive simulation results. Therefore, the proposed circuit is useful for the digital point-of-load application, with the key technical merit of PVT compensation without encountering the potential latch-up problem from the reported methods.

This paper presents a new performance-aware nanometer-scale MOSFET threshold voltage (VTH) measurement circuit that employs dual-segment nonlinear temperature compensation on the Brokaw circuit topology. Besides, a preregulator feedback control loop is used to enhance the power supply rejection (PSR) of the circuit. Fabricated in a UMC 65-nm CMOS process, it consumes 2.64 μW at 1.1 V supply. The measured results indicated that the VTH measurement circuit achieves an average temperature coefficient (TC) of 28.7 ppm/°C over 15 samples in a temperature range of -30 °C to 80 °C. PSRs of -54.5 dB at 100 Hz and -43.5 dB at 10 MHz are obtained without any output filtering capacitor. The average reference voltage is 470.3 mV, which is close to the extrapolated VTH for a low-threshold nMOS transistor at absolute zero.

This brief presents a sub-1-V 65-nm MOS threshold voltage monitoring-based voltage reference (VTHsensor) with current-mode second-order temperature compensation. By utilizing the different temperature properties of P+ diffusion and poly resistors, auxiliary nonlinear temperature compensation is implemented in the Brokaw MOS VTHcircuit. By doing so, it attenuates the nonlinear temperature effect of gate-to-source voltage (VGS), thus lowering the temperature coefficient (T.C.). Fabricated in a UMC 65-nm CMOS process, the results show that the circuit can generate an average reference voltage of 474 mV. This is close to the extrapolated VTHfor a low-threshold nMOS transistor at absolute zero temperature. In a range from -40 °C to 90 °C, the best T.C. achieved by the circuit is 24.5 ppm/°C and the average T.C. over 15 samples is 40 ppm/°C.

This paper presents an asynchronous sub-two-step circuit architecture to reduce the complexity and power consumption of internal analog-to-digital converter (quantizer) for Continuous-Time Sigma-Delta Modulator (CTSDM). By using the proposed new circuit topology, only 1/3 of comparators for a 5-bit quantizer design are needed when compared with the conventional flash based counterpart. The proposed quantizer has been implemented and fabricated in a UMC 65-nm CMOS process. The measured results have shown that the quantizer consumes 0.59 mW at an operating frequency of 250 MS/s in a 1.2 V supply and achieves 28.82 dB SNDR (4.5 ENOB) from the output spectrum.

An output-capacitorless low-dropout (OCL-LDO) regulator with a push-pull composite power transistor is presented in this paper. Using the proposed composite transistor, the nondominant parasitic poles can be pushed to higher frequencies, leading to good stability. In addition, the slew rate limitation at the gate of the power transistor is improved greatly by the proposed push-pull structure. Implemented and fabricated in UMC 65-nm CMOS technology, the LDO regulator occupies only an active area of 0.0096 mm2. The experimental results have shown that the regulator is able to operate at VIN = 0.75 V and deliver a maximum load current of 50 mA with a dropout voltage of less than 250 mV. It consumes a quiescent current of 16.2 μA and is able to settle within 1.2 μs.

An output capacitorless low-dropout (LDO) regulator, which applies the proposed Dual Summed Miller Frequency Compensation (DSMFC) on Flipped Voltage Follower (FVF) structure with composite power transistor, is proposed. Validated by UMC 65nm CMOS process, the simulation results have shown that the proposed LDO regulator consumes only 13.2μA at a 1.2V supply, with a dropout voltage of 200mV. At a total of 10pF compensation capacitance, it can support 0-50mA load current for a load capacitance range of 10pF-100nF at typical process and temperature whilst 10pF-10nF at worst condition. The proposed LDO regulator is able to recover in 0.925μs at CL=50pF. The comparison results have shown that the maximum load capacitance is more than two orders of magnitude with respect to those of the FVF LDO counterparts at identical process, supply, quiescent power and compensation capacitance.

This paper presents the random jitter and deterministic jitter analysis on the proposed polyphase filter (PPF)-based multiphase clock in frequency multiplier with reference to the benchmark jitter analysis of the multiphase clock counterpart using conventional delay-locked loop (DLL) approach. The analysis results have shown that the jitter performance of PPF-based design is better than that of DLL-based design. Jitter measurement on the PPF-based multiphase clock chip has been conducted. The overall comparison has shown excellent agreement among prediction results from theory and realistic simulation results from a combination of all the transistor-level circuits in conjunction with the proposed behavioral model. The comparison results confirm the proposed time domain jitter analysis method. The results have shown that not only do the PPF-based demonstrate the improved jitter performance, the deterministic jitter performance is also independent of components mismatch. Finally, the practical measurement results of the fabricated chip identifies the practical pitfalls of the proposed PPF-based DLL design, suggesting further jitter reduction and demonstrating the potential low-jitter design using the PPF-based DLL.