This paper proposes the use of coupled electric and magnetic circuits in the schematic models of high frequency integrated circuits, as an effective method to model the global inductive effects and coupling. These pairs of coupled circuits, called magneto-electro-equivalent circuit (MEEC) models, are obtained by partitioning the computational domain into several subdomains, each having its own electromagnetic field regime. The model reduction method we propose can be used not only to derive the full coupled electric and magnetic circuit model of a device starting from its layout, but also to correct the electric schematic by adding inductive parasitic effects. The MEEC approach uses special boundary conditions-called magnetic/electric hooks-on the interfaces between the subparts in which the computational domain is partitioned. The success of the correct extraction of inductive effects rely on the terminal reduction, i.e., the correct placement of magnetic hooks on the interfaces. In order to find this placement, a heuristic approach based on IC layout analysis is proposed. In order to consider the parasitic inductive couplings, the electric schematic circuit graph is enhanced with geometric information from the layout (e.g., node coordinates). The MEEC-based approach is validated for a real example of a low noise amplifier. Its initial layout design proved to be wrong only after the fabrication and characterization of the first prototype. The use of the inductive parasitic extraction tool, based on the MEEC approach, would have prevented this. MEEC is an alternative approach to vector potential equivalent circuit, with respect to which advantages and disadvantages are discussed.