Layout of a STAR device consists of the placement of standard cells (circuit elements) on the array and the routing of conductors between cells. Cell placement must be such that routing is not hindered. Also, placement procedures must be cost effective and easy to implement on a digital computer. A placement procedure for STARs is described in this paper that satisfies these characteristics. The procedure attempts to optimize the placement with respect to several criteria including expected routing channel usage and routing VIA requirements. Computer implementations of the procedure are discussed. Experimental results are presented which indicate that the procedure yields near-optimum results in computationally convenient amounts of time.

A system for collecting data on COBOL source programs corresponding to the input parameters of various software reliability models is described in this paper. The system is described in terms of information sources, program functions, data base file structures, and reports generated.

A generalized test function (GTF) is derived that gives all tests for a multiple stuck-at fault in a combinational logic circuit. The GTF is then used as the basis for an examination of several algebraic test generation methods that have appeared in the literature. Deficiencies are found in some methods.

This paper deals with the synthesis of two-level networks of threshold gate logic elements for realization of nonlinearly separable switching functions. The realization obtained contains the minimum number of threshold logic elements possible for a two-level realization. An algorithm based on the tree procedure of Coates and Lewis is developed which can be used to obtain the desired network realization for a given switching function. The function may be incompletely specified.