In this article, we propose a new robust and highly efficient digital predistortion (DPD) concept for the linearization of wideband RF power amplifiers (PAs). The proposed approach is based on the combination of a parallelized delta-sigma modulator (DSM) and a forward model of the PA. This concept applies multi-rate techniques on a DSM that incorporates the forward PA model in its feedback loop to perform the required signal predistortion. Such a technique eliminates the need of reverse modeling and its associated problems. The multi-rate approach relaxes enormously the clock speed requirement of the DPD, which allows handling high signal bandwidths at feasible sampling rates. Moreover, enhanced performance can be achieved without the need of increasing the order of the modulator which reduces the sensitivity of the system to gain variations and phase distortions caused by the nonlinear PA characteristics. Three time-interleaved parallel DPD (P-DPD) variants are described and introduced, all of them have been shown to offer increased accuracy, and consequently better linearization performance compared to the DSM-based DPD state-of-the-art. The proposed architectures are tested and assessed using extensive real-world RF measurements at the 3.6 GHz band utilizing wideband 100 MHz 5G New Radio (NR) transmit waveforms, evidencing excellent transmit signal quality.

This article presents two novel digital predistortion (DPD) based architectures that jointly mitigate the inphase/quadrature (IQ) modulator impairments and the power amplifier (PA) nonlinear distortion in wireless transmitters. The proposed architectures are multibit cartesian and complex delta-sigma modulator-based joint DPDs, called CDSM-JDPD and CXDSM-JDPD, respectively, which enable using low-cost digital-to-analog converters (DACs) while offering versatile linearization capabilities to combat the coexisting distortions of the PA and the IQ modulator. The proposed approach alleviates the need for reverse modeling and implementation of extra hardware to separately deal with frequency-dependent IQ impairments. Moreover, the CXDSM-JDPD enhances the linearization performance and relaxes the high oversampling ratio (OSR) requirement by quantizing the signal more efficiently. Furthermore, the presented concepts inherently support the use of low-resolution DACs, which offers a tremendous advantage in designing and implementing low-cost and energy-efficient radio transmitters. Extensive set of hardware-in-the-loop RF verification measurements with a commercial PA are provided, including two timely 5G New Radio (NR) scenarios at NR bands n3 and n78, while covering channel bandwidths up to 100 MHz and varying the OSR and the DAC bit resolution. The obtained results demonstrate the excellent linearization capabilities of the proposed solutions and their superiority compared to other DSM-based DPD approaches.

In this paper, new digital predistortion (DPD) solutions for power amplifier (PA) linearization are proposed, with particular emphasis on reduced processing complexity in future 5G and beyond wideband radio systems. The first proposed method, referred to as the spline-based Hammerstein (SPH) approach, builds on complex spline-interpolated lookup table (LUT) followed by a linear finite impulse response (FIR) filter. The second proposed method, the spline-based memory polynomial (SMP) approach, contains multiple parallel complex spline-interpolated LUTs together with an input delay line such that more versatile memory modeling can be achieved. For both structures, gradient-based learning algorithms are derived to efficiently estimate the LUT control points and other related DPD parameters. Large set of experimental results are provided, with specific focus on 5G New Radio (NR) systems, showing successful linearization of multiple PA samples as well as a 28 GHz active antenna array, incorporating channel bandwidths up to 200 MHz. Explicit performance-complexity comparisons are also reported between the SPH and SMP DPD systems and the widely-applied ordinary memory-polynomial (MP) DPD solution. The results show that the linearization capabilities of the proposed methods are very close to that of the ordinary MP DPD, particularly with the proposed SMP approach, while having substantially lower processing complexity.

This paper studies the idea and performance of cyclostationary spectrum sensing in cognitive full-duplex radios, when secondary transmission and spectrum sensing are done simultaneously at the same channel. The paper starts by briefly introducing the ideas of cognitive full-duplex radio and the cyclostationary spectrum sensing in the presence of self-interference. The idea of changing the cyclic features of the secondary signal is then proposed and its impact on the spectrum sensing under self-interference is analysed. The cyclic features can be changed by changing the length of the cyclic prefix of the OFDM signal or by changing the amount of subcarriers. The effects of both approaches are evaluated with comprehensive performance simulations. It is shown that changing the cyclic features of the secondary signal can provide significant improvements in the sensing results of the primary signal, and that in general, reliable inchannel spectrum sensing while transmitting is feasible. This can enable enhance coexistence mechanisms, e.g., for LTE-Unlicensed technology at ISM band.

This article proposes a reconfigurable wideband transfer function design for quadrature ΣΔ A/D converters combined with digital post-compensation of frequency-selective mirror-frequency interference (MFI) induced by the inherent mismatches between the in-phase (I) and quadrature (Q) rails of the receiver. When receiving wideband waveforms, e.g., similar to LTE signals, it is crucial for the compensation performance to be able to consider also frequency variations in the image rejection. In addition to compensating the MFI originating from inside the quadrature ΣΔ modulator (QΣΔM), the digital compensation considers also the interference generated at the preceding receiver front-end components, such as an I/Q mixer. The performance of this approach is illustrated with a 20 MHz reception bandwidth, being a practical example of requirements for modern communications waveforms. This concrete example is given with a two-stage QΣΔM giving eighth order noise-shaping.

A quadrature ΣΔ analog-to-digital converter (ADC) is a promising solution for intermediate frequency digitizing software defined cognitive radio (CR) receivers because of, e.g., multiband capability and power efficiency. However, inherent coefficient mismatches between the in-phase and quadrature rails can severely damage the performance of such receiver by creating mirror-frequency interference (MFI). In this article, a novel frequency-agile and reconfigurable transfer function design, allowing digital post-compensation of the MFI, is proposed. The design is based on a novel closed-form transfer function model for higher-order quadrature ΣΔ modulators (QΣΔMs) under implementation inaccuracies, proposed herein. By doing the compensation in digital domain, it is possible to take into account all error-sources of the receiver chain at once, including, e.g., a quadrature mixer before the ADC. This capability is obtained by preserving the mirror-band signal information and using the noise transfer function of a QΣΔM to remove quantization noise from therein. This is demonstrated in a multiband scenario aimed for CR receivers, where a number of frequency channels can be received and detected in parallel. Practical examples of the transfer function analysis under implementation inaccuracies and the post-compensation performance are given with a two-stage QΣΔM, having stage-orders of four, allowing eighth-order noise shaping.