For wireline transmitters (TX), the traditional architecture would introduce a large amount of parasitic capacitance and reduce the bandwidth of the output stage. Strict timing constraints for retiming units in FFE arrays would also limit speed and consume extra power. In this paper, we propose an analog-MUX-based architecture with a small capacitance load of output drivers and inherent FFE without strict timing constraints. Only one full-speed node makes it easy to use inductors to extend bandwidth. The expanded output bandwidth ensures the TX to reach a comparable operating speed with advanced technology even in traditional planar technologies. A CML clock path with switched inductors is proposed to cover the full frequency band. Implemented in a 65nm CMOS process, the TX with 112Gb/s PAM4 data rate and 3.14pJ/bit efficiency is achieved. The data rate can be further improved with more advanced process nodes.

This paper analyzes the relationship between the total output noise power and loop filter coefficients variation of continuous-time delta-sigma modulators. Based on the analysis, a new calibration technique utilizing the total output noise power to improve the loop filter inaccuracy caused by PVT variation is proposed. This proposed calibration method is implemented in the digital domain and requires only capacitor arrays in analog loop, minimizing the hardware cost and the excess loop delay. The calibration technique is verified by a third-order delta-sigma modulator post-layout simulation results. The peak signal-to-noise-and-distortion ratio (SNDR) increased by 4.5dB after calibration.

Delay solutions applied to high frequencies typically involve switched transmission lines or all-pass filters. These solutions often suffer from significant insertion loss and drastic gain variations at high frequencies, along with poor delay flatness. In this work, we have designed a delay circuit that can be applied to high frequencies, featuring excellent delay flatness, good delay resolution, and a wide bandwidth. In this design, a multistage cascaded sampling circuit is used to generate delays. By introducing differential clocks or three-phase clocks, simple coarse delay or fine delay can be achieved. The measurement results show that the sample and hold circuit achieves a delay accuracy of 17.5 ps and a delay range of 453 ps within 0.5–2.5 GHz, with a gain of −2.7 to 2 dB and a gain variation of ±0.85 dB, a delay variation less than 7.5 ps, a power consumption of 111 mW, and a core area of 0.137 mm2.

This paper presents a multi-band front-end module (FEM) with a built-in transmit/receive (T/R) switch in 28 nm standard CMOS technology for 5G NR communication. A T/R switch topology is proposed to separate the design processes of the power amplifier (PA) and the low noise amplifier (LNA), which reduces the insertion loss in Tx mode caused by the T/R switch. To enable cover the all 5G NR bands at 28 GHz and 39 GHz, a four-coupled inductor-based reconfigurable inductor is used to shift the operational band in the interstage matching network of the low noise amplifier (LNA) and power amplifier (PA). Identical signal paths are used for both the LNA and PA. The FEM consists of a two-stage pseudo-differential PA with a cascade output stage to obtain high output power, a single-end LNA with two-stage cascade to achieve high power gain, and a compact and relatively low insertion loss T/R switch. The measured OP1dB and PAEOP1dB in Tx mode are 17.42 dBm and 16.36%, respectively. The measured NFmin in Rx mode is 5.65 dB. A 64-QAM 600 MSym/s single-carrier was measured in Tx mode.

This article presents two Ka-band low-noise amplifiers (LNA) for millimeter-wave (mm-wave) phased-arrays. The folded three-coil transformer and electrical-magnetic (EM) dual-feedforward techniques are proposed to improve the LNA’s noise performance and reduce the chip area. Design procedures targeting compact chip area, low noise, and high gain are provided. The first two-stage single-ended LNA, consisting of a common-gate (CG) input stage and a common-source (CS) output stage, achieves 1.9 dB minimum noise figure (NF), 16.7 dB peak gain, 4.3 GHz 3 dB bandwidth (BW) from 25.6 to 29.9 GHz, and$-$12 dBm input 1-dB gain-compression-point (IP1dB) with 13.2 mW power consumption. The second LNA employs the current-reuse topology based on the first LNA, which reduces the power consumption to 3.6 mW at the cost of 0.6 dB NF degradation. The proposed LNAs have been fabricated in 65 nm CMOS process. The two LNAs have the same 200$\mu $m$\times$300$\mu $m core chip area. To the best of our knowledge, the first LNA shows the lowest NF and smallest core area at 28 GHz compared with the published CMOS works in a similar frequency range.

An IEEE 802.15.4/4z standard compliant all-digital UWB transmitter with a fast-settling master-slave voltage regulator is presented in this paper. The proposed digital transmitter (DTX) with the master-slave regulator reduces the power supply crosstalk from the all-digital transmitter operation, which contributes to maintaining decent TX power spectral density (PSD). In addition, the deterioration of DTX PSD is avoided by synchronization of the data stream in the LO domain and the alignment of AM/PM paths in the DTX. Furthermore, wide-band transformer-based impedance matching is introduced in the DTX to achieve high output power with high efficiency while performing the differential-to-single-ended conversion. The presented UWB DTX has been designed in a 28nm CMOS and covers from 6.5 to 8 GHz (Ch5 to Ch9). The DTX achieves 13-dBm TX peak power. The transmitted pulse complies with FCC and ETSI regulations achieving 71% spectrum efficiency and -32-dBr sidelobe suppression.

This article presents a compact 24–30-GHz four-element phased-array transceiver (TRx) front-end (FE) for 5-G communications. A compact T/R switch co-designed with power amplifier’s (PA) output matching network and low-noise amplifier’s (LNA) input matching network is proposed. Leveraging the transformers in the two matching networks, only one extra transistor switch is needed, which greatly reduces the chip area consumption and therefore the insertion loss. A bidirectional phase shifter composed of a two-stage polyphase filter (PPF) and two bidirectional variable-gain amplifiers (BVGA) is shared by both TX and RX. The 24–30-GHz four-element TRx FE is implemented in 65-nm CMOS process. The TX path including the power splitter and T/R switch achieves a measured 11.5-/16.5-dBm OP1dB/PSAT with 12.2%/22.9% PAE$_{\mathrm {1 dB}}$/PAEMAX with 35.1-dB gain. The RX path including power combiner, T/R switch, and off-mode PA achieves a minimum 5.1-dB noise figure (NF) with 25.8-dB gain. The TX and RX paths achieve 5.625° phase resolution with$ < 2^{\circ }$/0.4-dB rms phase/gain error as well as 30.6-dB gain control range with 0.5-dB gain step and$ < 1.5^{\circ }$/0.26-dB rms phase/gain error over 24–30 GHz. Under the 64-QAM fifth-generation (5G) NR FR2 orthogonal frequency division multiplexing (OFDM) measurements, the TX path achieves an average output power of 0 dBm per element (2.1% PAE) with 8.66% EVM, and the RX path achieves an average 4.96% EVM, making the proposed TRx FE suitable for 5G NR FR2 applications. The chip size excluding pads is$4.1\times4.0$mm.

This paper presented a 76–81 GHz FMCW MIMO Radar transceiver with mixed-mode PLL. Utilizing series-fed patch antenna array, a prototype system is developed based on the proposed transceiver. On-chip Measurements show that reconfigurable sawtooth chirps could be generated with a bandwidth up to 4 GHz and a period as short as 30${\mu s}$. Real-time experiments demonstrate that the prototype MIMO radar has the ability of target detection and achieves an angular resolution of 9°

This work presents a linearized Ka-band heterodyne receiver for millimeter-wave phased-array systems with high linearity requirement. A folded class-AB inductive peaking mixer and a two-stage magnetic self-cancellation-based load-pull interstage matching Intermediate-frequency (IF) amplifier are proposed to improve the linearity of input and output 1-dB compression point, respectively. The proposed receiver is implemented in 65 nm CMOS technology and its core area is 0.7 mm2. The measured input 1-dB compression point (IP1dB) is −10.9dBm and the output 1-dB compression point (OP1dB) is 7.1 dBm, with noise Figure (NF) of 10.1 dB at center frequency. To the best knowledge of the authors, the proposed RX achieves the highest IP1dBand OP1dBamong all the listed publications in silicon technology. The power consumption of the receiver including LO path is 119mW.

An energy-efficient millimeter-wave transceiver with direct-modulation digital transmitter (TX), I/Q phase-coupled frequency synthesizer and Substrate-Integrated Waveguide (SIW) E-shaped patch antenna is presented in this paper. The proposed transceiver achieves the 10-Gbps data rate while consuming 340.4 mW. The measured Over-the-Air (OTA) EVM is -13.8 dB. The energy efficiency is 34 pJ/bit, which is a significant improvement compared with the state-of-the-art mm-wave transceivers.

A 35-GHz transmitter (TX) and receiver (RX) front-ends in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers is presented in this paper. In order to mitigate undesired electromagnetic coupling through LC resonators in TX/RX and avoid severe metal density issue in highly scaled CMOS technology, Ka-band RF circuit design strategy using transmission line is studied. To improve the TX output power level, a power amplifier (PA) with 4-way power splitter/combiner and transmission line for impedance transforming is introduced. The proposed TX and RX front-ends is designed and fabricated in a 65nm CMOS technology. The measured TX output power is 19 dBm. The RX achieves a conversion gain of 29.6 dB. The TX occupies 1.42 mm2and consumes 588 mW. The RX occupies 0.59 mm2and consumes 72mW.

A 4.25-4.65 GHz LC-VCO with tailing filter technique integrating an 8-shaped inductor with an orthogonal-coupled tail-filtering inductor is presented in this paper. The mutual inductance between the 8-shaped inductor and the tail-filtering inductor is negligible due to the symmetrical and reversal magnetic field by the two loops of the 8-shaped inductor, which avoids the additional chip area occupation of the bulky tail-filtering inductor. The VCO is implemented in TSMC 180 nm CMOS process, obtaining a tuning range (TR) of 0.4 GHz, which consumes 7.7 mA current from a 1 V power supply. By adopting the 8-shaped inductor and noise filtering technique from the orthogonal-coupled inductor, the post-layout simulated phase noise achieves -126.7 dBc/Hz at 1 MHz offset away from the 4.4 GHz carrier and the resulting figure-of-merit (FoM) is -191 dB.

A 35-GHz transmitter (TX) and receiver (RX) front end in CMOS technology for Ka-band frequency-modulated continuous wave (FMCW) phased-array radar transceivers are presented in this article. While typical FMCW phased-array radar transceivers use RF-path phase-shifting scheme for both TX and RX front ends, the Ka-band TX and RX front ends presented in this article are designed for TX-analog and RX-digital beamforming phased-array radar system. The link budget for the Ka-band phased-array radar transceiver is investigated. In order to improve the TX output power level, a power amplifier (PA) with a four-way power splitter/combiner is introduced. The detailed analyses and design considerations of the PA are investigated. The proposed TX and RX front ends are implemented and fabricated in a 1P9M 65-nm CMOS technology. The measured TX output power is 19 dBm. To the best of authors' knowledge, it is the highest output power FMCW module at the Ka-band using CMOS technology reported so far. The RX achieves a conversion gain of 29.6 dB. The TX occupies 1.42 mm2and consumes 588 mW. The RX occupies 0.59 mm2and consumes 72 mW.

An ultra-wide band, high linearity and low phase noise 43 GHz voltage-controlled oscillator (VCO) for frequency-modulated continuous-wave (FMCW) radar system is presented. A transformer-based magnetic-tuning technique is adopted to realize both coarse frequency tuning and fine frequency tuning, achieving a sweeping bandwidth of >5.7 GHz within single tuning curve. Distributed biasing parallel varactors are used to achieve high tuning linearity. Since the flicker noise (1/f noise) significantly worsens the VCO phase noise due to high 1/f corner frequency in TSMC 28nm CMOS, a technique to suppress the flicker noise up-conversion is adopted to improve the phase noise performance. The VCO has been implemented in TSMC 28 nm CMOS process, obtaining a tuning range (TR) from 37.5 GHz to 49 GHz, which consumes 8 mA current from a 0.95 V power supply. The phase noise is lower than -100 dBc/Hz at a 1 MHz offset from a 37.5 GHz carrier and the resulting FoM is -182 dBc/Hz.

An analog solution of the capacitor-less low dropout regulator (CL-LDO) using the adaptive DC level shift (ADLS) and bulk-driven feed-forward (BDFF) techniques is proposed. The ADLS circuit is adopted to increase the headroom of the pass transistor's gate voltage, which achieves a larger current loading capability without increasing the size of the pass transistor. The BDFF technique decreases the threshold voltage of the pass transistor to improve its current driving capability and expand the bandwidth of the power supply rejection ratio (PSRR) by adding a feed-forward path at the pass transistor's bulk. The proposed LDO has been implemented in TSMC 28nm CMOS. The simulation results show that the proposed CL-LDO consumes 308 μA current from a 1.2-2.5V power supply, with a 0.7 to 0.9V output range. With 2pF internal capacitance, it can support 0-50mA load current within 80pF load capacitance range. The PSRR is under -20dB across 5MHz frequency range.

An integrated 21.4-22.4 GHz fractional-N phase-locked loop (PLL)-based frequency synthesizer with low phase noise LC voltage-controlled oscillator (VCO) is implemented for a RF receiver in wireless communication systems. The K-band VCO generates a signal with a phase noise that is lower than -93.4 dBc/Hz at 1 MHz offset frequency, using a current source filtering technique to improve the phase noise while having a 11% tuning range. The VCO achieves a figure-of-merit (FOM) of -179.5 dBc/Hz with a power consumption of 16 mW. The transient mismatch of the charging and discharging current in the charge pump is optimized about 0.1% in the typical case, which minimizes the steady-state phase error in the PLL. The PLL outputs a signal with a phase noise that is lower than -97.5 dBc/Hz at 1 MHz offset frequency with a total power consumption of 53 mW in 90 nm CMOS.

A fractional-N frequency divider based on a 5-bit phase interpolator (PI) is presented in this paper. A novel PI unit cell with the switched resistor loads is proposed to break the constraint brought by the variation of the common-mode output voltage, providing an extra design degree of freedom for the optimization. An all-digital phase rotating scheme is proposed to achieve an excellent balance between the robustness of the phase interpolation and the speed limitation of the synthesized phase control circuit. The proposed fractional-N frequency divider is designed in 65-nm CMOS technology, dissipating 1.13-1.3 mW from a 1.2-V supply with the quadrature input signals at 2.4 GHz. To further evaluate the influence of the PI non-linearity, a behavioral simulation model based on Simulink is built. The behavioral simulation results show that the in-band spur induced by the fractional-N frequency divider is -51.8 dBc.

A flexible continuous-time ΔΣ modulator that supports both low-pass and complex bandpass (CBP) architectures with the programmable bandwidths of 5 and 10 MHz is presented. By utilizing flexibility into both architectural level and core building blocks, scalable power consumption is obtained for each mode with desired performance. An amplifier topology with active feedforward, antipole splitting, and current reuse techniques is proposed for effective power reduction. A prototyped ΔΣ modulator in a 65-nm CMOS achieves a 65.1-/62.2-dB peak signal-to-noise-plus-distortion ratio (SNDR) with a 5-/10-MHz bandwidth in the LP architecture and a 62.9-/64.1-dB SNDR over a 5-/10-MHz signal band with a tunable center frequency of 4-6 MHz in the CBP architecture, respectively. The figure of merit is 0.21/0.23/0.36/0.24 pJ/conversion step for each mode with a power consumption of 3.1/4.8/4.2/6.3 mW by a 1.2 V supply voltage. The dynamic range is 73/65.8/74.3/74.2 dB. The active area is 0.39 mm2.

An interference-robust reconfigurable receiver in 65-nm CMOS is presented. The front end is split into a lowband (LB) RF path (0.1-1.5 GHz) and a high-band (HB) RF path (1-5 GHz). By utilizing a harmonic recombination technique, the LB path could reject the third /fifth-order harmonic interferences. A tunable narrowband dual-feedback common-gate low-noise amplifier (LNA) with LC resonant load provides second-order bandpass filtering to reject the harmonic interferences in the HB path. The RF high-Q bandpass filtering based on the voltage-mode passive mixer and the current-mode low-pass filter in the analog baseband improves the receiver's resilience to out-of-band interferences. A novel power-detectionbased automatic frequency calibration technique is proposed to calibrate the operating frequency of the LNA in the HB path and overcome the effects of process, voltage, and temperature variations. The presented receiver has been implemented in a 65-nm CMOS and consumes 20-76-mW power from 1.2-V power supplies, with a core die area of 5 mm2. The measured results show that the receiver can tolerate -5-dBm interference with 16-dB noise figure (NF) and achieve 95-105-dB maximum conversion gain and 1.7-8-dB NF over 0.1-5 GHz. It also achieves an average harmonic rejection (HR3)/HR5 of 61/68dB, +7.1/+14.4 dBm in-band/out-of-band input third-order intercept point (OB-IIP3), +71.2-dBm OB-IIP2, and 58.1-dB-image rejection, after the digitally assisted calibrations. The systemlevel measurements show that the presented receiver achieves 2.1% error vector magnitude (EVM) for 850-MHz Global System for Mobile Communication signals and 5% EVM for band 42 time division duplexing-local thermal equilibrium (LTE) signals, respectively.

A reconfigurable IF receiver supporting intra-band non-contiguous carrier aggregation is proposed. By utilizing the harmonic rejection (HR) mixer with 12-phase LOs and phase-shift-adding configuration, the IF receiver could eliminate the channel interferences, which is robust to the mismatch. The IF receiver has been implemented in 65nm CMOS, and the simulate d results show that the interference between different channels is below -59dBc, and the IF receiver achieves -12.16dBm-6.52dBm input P1dB, with 21.71mA~23.39mA current consumption from one 1.2 V power supply.

A dual-mode second-order reconfigurable quadrature bandpass continuous-time delta-sigma modulator is presented for a low-IF global navigation satellite system receiver to simplify the entire architecture. The proposed modulator is capable of supporting both narrowband of 5-MHz bandwidth (BW) and wideband of 20-MHz BW. An amplifier topology with active feed-forward and antipole-splitting compensation schemes is proposed. The flexible amplifiers in active-RC integrators and preamplifiers in comparators are implemented with power scaling technique to effectively adjust the power consumption for both BWs. A 1-bit digitally switched current digital-toanalog converter structure with gate-leakage compensation and low-latency dynamic element matching is proposed to cover large current variations and mitigate the gate-leakage issue. Digital I/Q self-calibration algorithm is realized to improve the imagerejection ratio (IRR). Implemented in 65-nm CMOS, the ΔΣ modulator achieves 67.8-/61.4-dB dynamic range, 65.9-/53.7-dB signal-to-noise-plus-distortion ratio, and >60-dB IRR after calibration across 5-/20-MHz BW with center frequencies of 4/12 MHz, respectively. Powered by a 1.2 V supply, the modulator only consumes 4.2/8.1 mW, resulting in measured figure-of-merits of 0.26/0.51 pJ/conversion step.

A 0.5-30GHz wideband differential CMOS T/R switch is proposed with low insertion loss (IL), high power handling capacity and high TX-RX isolation. The independent bias technique is proposed to keep the transistors in ideal on/off mode to improve IL and power handling capacity. The leakage cancellation technique is introduced to cancel leakage from TX port to RX port with two match paths. The proposed T/R switch has been implemented in 65nm CMOS, and simulation results show that it achieves 1.2/1.9dB IL and 43/31dBm 1-dB compression point (P1dB) in TX/RX mode and 60dB TX-RX isolation over 0.5-30GHz.

A 4.8-mm20.1-6.0-GHz dual-path software-defined radio transmitter supporting intraband carrier aggregation (CA) in 65-nm CMOS is presented. A simple approach is proposed to support intraband CA signals with only one I-Q baseband path. By utilizing the power-scalable and feedforward compensation techniques, the power of the wideband analog baseband is minimized. The transmitter consists of a high gain-range main path and a low-power subpath to cooperatively cover different standards over 0.1-6.0 GHz with more flexibility. The reconfigurable power amplifier (PA) driver achieves wideband frequency coverage with efficiency-enhanced on-chip transformers and improved switched-capacitor arrays. This transmitter achieves <;-50-dBc image rejection ratio and <;-40-dBc local oscillating signal leakage after the calibration. System verifications have demonstrated -31/- 51-dBc ACLR1/ACLR2 (adjacent channel leakage ratio) at 3-dBm output power for 2.3-GHz LTE20 in the main path and 1.7% error vector magnitude (EVM) at 1.5-dBm output for 1.8-GHz WCDMA in the subpath. Both paths enable SAW-less FDD operations with -153 or -156 dBc/Hz carrier-to-noise ratio at 200-MHz frequency offset. Finally, the dual CA signals with 55-MHz frequency spacing are verified, showing the EVM of 1.2% and 0.8%, respectively, and exhibiting the intraband CA capability.

A multi-mode reconfigurable analog baseband with I/Q calibration for GNSS receivers is presented. The baseband circuit consists of an I/Q calibration circuit, a reconfigurable complex band-pass filter (C-BPF) and an AGC loop. It provides I/Q mismatch auto-calibration with the aid of a FPGA. The 3rd/ 5th-order reconfigurable C-BPF supports various bandwidths from 2.2 to 10 MHz and with different center frequencies from 3.996 to 16 MHz. The AGC loop features 5-50 dB gain range and 1 dB step, and digital AGC algorithms. The auto DC-offset cancellation is also integrated on-chip. The analog baseband circuit has been implemented in 180 nm CMOS and consumes 6.5-13 mA variable current thanks to the power scaling technique. The measured image-rejection ratio is 45-55 dB, improved by 22 dB after I/Q calibration.

This paper reports a new scalable behavioral modeling technique for silicon controlled rectifier (SCR) based electrostatic discharge (ESD) protection structures using Verilog-A language. Accurate models were developed for various low-triggering voltage SCR ESD (LVSCR) protection structures implemented in a foundry 180nm RF process, which were validated by circuit simulation and ESD measurement.

This paper presents a 65nm multi-mode complex band-pass filter (C-BPF) used in low-IF GNSS receivers. It supports the bandwidth of 4MHz, 10MHz and 18MHz, and can be centered at 4.2MHz, 6.1MHz, 12.3MHz and 28MHz. The OTAs served in the filter are realized in arrays which makes the power consumption scalable among different operation modes. In addition, assistant transconductors (assistant-gm) are adopted to compensate the outputs of each OTA stage, which in turn saves at maximum 9mA DC current for the whole filter. In order to achieve higher than 30dB image rejection ratio (IRR), another group of assistant-gms are introduced to the input stage for I/Q mismatch calibration, which is able to regulate a maximum ±3dB amplitude imbalance and ±5° phase imbalance. The filter consumes less than 10mA in the 28MHz-IF, 18MHz-bandwidth mode, and achieves >31dB IRR with the maximum I/Q amplitude and phase mismatch.

We report design and analysis of full-chip ESD protection solution for high-voltage (HV) mixed-signal ICs in a BCD30V technology by mixed-mode ESD simulation involving integrated process, device, circuit and layout co-design. The full-chip HV ESD protection scheme includes both I/O and power clamp ESD protection. Mixed-mode ESD simulation technique enables pre-Si ESD design optimization and prediction. ESD measurements confirm full-chip HV ESD protection of >4.5KV for the whole chip. This design technique can be applied to practical full-chip HV ESD protection circuit design for mixed-signal ICs in various HV BCD technologies.

A half-rate clock and data recovery (CDR) circuit for 60GHz communication with 20Gbps QPSK modulation in 65nm CMOS is presented. A hybrid DC-offset cancellation loop (DCOC) is proposed to calibrate the input offset. A duty cycle distortion (DCD) cleaning up circuit is adopted to minimize the negative impact on the half rate sampling in the CML-CMOS conversion, and a quadrature clock calibration (QCC) is utilized to correct the input clock I/Q phase mismatch. The CDR is based on phase interpolator (PI) and uses the quadrature clocks from the divider of the main PLL. The whole CDR consumes less than 16mW with 1V power supply and achieves less than 1mV DC-offset, 0.2% DCD and less than 1° residual I/Q phase mismatch after calibration.

A multi-mode reconfigurable wideband continuous-time lowpass/quadrature bandpass sigma-delta (CT LP/QBP ΣΔ) modulator employing power scaling technique (PST) for LTE-advanced/industry-specialized zero/low-IF receivers is presented. The proposed modulator consists of a loop filter with active-RC integrator configured as 3rd-order lowpass or 2nd-order complex bandpass architecture and 4-bit internal quantizer operating at 80MHz, 160MHz and 320MHz, respectively. A programmable differential current-steering DAC unit is adopted for high linearity. In LP mode, the excess loop delay is set to half the sampling period of the quantizer and an additional feedback DAC is used to maintain stability, which is not used in QBP mode. The modulator employs flexible high gain and high bandwidth amplifiers with PST to optimize power consumption among various modes. Implemented in 65nm CMOS, the modulator achieves 84.8/85.8/84.5dB SNDR, 94.9/94.1/94.6dB SFDR over 2.5/5/10-MHz signal bands in LP modes and 83.8/ 84.6dB SNDR, 94.3/96dB SFDR across 2.5/5-MHz bandwidth with programmable center frequencies of 2/4-MHz in QBP modes, respectively. Powered by a 1.2-V supply, the modulator consumes 1.8 to 4.2mW, which results in simulated FOMs of 15.5 to 27.8fJ/conversion.

This paper presents a power detection based I/Q imbalance self-calibration technique to compensate signal path gain and phase mismatch in a reconfigurable low-IF receiver. The calibration can be carried out at startup to improve the image rejection ratio (IRR) of the IF complex-bandpass filter, and then configuration words are saved. The system employs an analog I/Q calibration module to adjust signal path gain and phase mismatch, a power detector to measure I/Q imbalances, digital circuits to implement the calibration algorithm, and a digital AGC to adjust IF signals within a predetermined level. The self-calibration system is implemented as a part of a multi-mode GNSS (Global Navigation Satellite Systems) receiver. Only one 2-bit ADC in I (or Q) path is needed to sample the analog IF signal. Measurement results show that the calibrated IRR achieves an average of 50dB in different operation modes which gets a 10~20dB improvement. The low-IF GNSS receiver is fabricated in 65nm CMOS process, and the digital part of the self-calibration system is implemented in a FPGA.

A 0.13 um CMOS 1.5-to-2.15 GHz low power transmitter front-end with direct quadrature voltage modulation for SDR applications is presented. The SDR transmitter front-end consists of PGA, passive RC filter, direct quadrature voltage modulator, 25%-duty-cycle LO generator and programmable PA-Driver with reconfigurable operation frequency bands. An on-chip transformer with switched- capacitor array provides the wide-band reconfigurable frequency band covering and differential-to-single-ended conversion. The passive voltage mixer with 25%-duty-cycle LO implements the frequency up-conversion with low noise and low conversion loss. The SDR transmitter front-end has been implemented in 0.13 um CMOS, the measured results show that this front-end could provide 22 dB gain with a step of 2dB and output higher than OdBm power across 1.5-to-2.15 GHz frequency range with a maximum power consumption of 42 mW. The die area is 1.6 mm* 1.2 mm.

Techniques are proposed to enhance the bandwidth of ultra-wideband (UWB) CMOS low-noise amplifiers (LNA). By using multiple-input-branch technique and resistive shunt-feedback technique, LNA could achieve ultra-wideband input impedance matching with small noise figure degradation. The gain bandwidth is enhanced by an L type inter-stage matching network between the input transistors and the cascode transistor which could enhance both the gain and the gain bandwidth. The gain bandwidth could be further enhanced by the resistors inserted between the bulks and the sources of the input transistors since the resistors could reduce the effects of the drain-bulk capacitance of the input transistors. The techniques proposed offer the advantages of ultra-wideband bandwidth, simple circuit topology, and small chip area. The proofs of techniques are demonstrated by designing the UWB LNA in UMC 0.18um CMOS.

In this paper, an improved method of power control is introduced to widen the range of output power with high efficiency. Two CMOS class-E power amplifiers (PA) with different output power are adopted in the design. In order to eliminate the phase mismatch of two paths, a continuously adjustable CMOS phase shifter with a predictable phase transfer function is added before each PA. Meanwhile, the drain modulation technique is presented to vary the voltage supply of the amplification unit. With the combination of drain modulation and parallel amplification, a wider range of output power is obtained than the previous one. The amplifiers work in 915MHz with the supply voltage of 1.8V and 2.5V. Simulation results show that the amplification unit could reach a maximum output power of 26dBm and maintain a power-added efficiency (PAE) higher than 40% over the 18dBm–26dBm output power range.

In this paper, a novel architecture of a fractional-Nphase-locked loop (PLL) is presented for digital clock generation. By employing multimodulus dividers in parallel with sequential outputs of a ΔΣ modulator, finite impulse response (FIR) filtering with respect to modulator noise is realized in the PLL, resulting in quantization noise reduction in high frequencies. Hence, a low oversampling ratio (OSR) ΔΣ fractional-NPLL can be achieved without increasing quantization noise. Architecture comparison and simulation results are also presented.

A 0.18mum CMOS 2.4GHz LNA (low noise amplifier) with digitally switchable capacitance has been designed to investigate its ability to compensate for performance variation across worst case process conditions. The effects of transistor model and passive component variation are first simulated to quantify the range of performance uncertainty. The use of various methods of switchable capacitance is then investigated at multiple LNA nodes to observe the effect on S11, S21, and NF. After calibration, the new design allows for 300MHz of frequency tuning and improvements in S11by 7.2dB, S21by 2.4dB, and NF by 0.6dB.

In this paper, a CMOS class-E power amplifier with power control is presented. Its output power could be varied over a broad range with high efficiency by utilizing the combination of the parallel amplification technique and the drain modulation technique. The drain modulation is implemented as a class-S modulator and the output powers of the parallel amplifiers are combined with quarter-wavelength transmission lines. The simulation results show that the power amplifier could achieves a maximum power-added efficiency (PAE) of 47.9% and maintain a PAE higher than 41% over the 140-700mW output power range.

A fully-differential 2-GHz phase-locked loop (PLL) was designed and fabricated in 0.18-μm CMOS process. The PLL rejects the common noise due to fully-differential VCO and differential charge pump. The VCO has a 16.15% tuning range (from 1.8998GHz to 2.2335GHz) due to a combination of analog and digital tuning technique (4-bit binary switch-capacitor array). With the pn-junction varactors, the phase noise of the VCO varies only about 2dB in the tuning range. The current consumption of the PLL is only about 6.1mA from a 1.8V power supply. It is comparable to the results reported in recent literatures. The phase noise of the PLL at 2.033GHz can achieve -117.17dBc/Hz at 1 MHz frequency offset from the carrier.

A CMOS down-conversion micromixer for IEEE 802.11b WLAN transceivers is presented. The micromixer is a class-AB single-ended input double balanced mixer with on-chip bias loop. The operating principle of the CMOS micromixer is quantitively discussed and some design insights are given out. The mixer has been implemented in 0.18/spl mu/m CMOS process. The measured results show that the mixer achieves 1.5dB conversion gain, 12.2dB SSB NF, -1.5dBm input P1dB, 4dBm IIP3 with -16dB S11 (2.45GHz RF, 280MHz IF). The mixer draws 5.7mA current from a power supply of 1.8V.

This work presents the design and implementation of a 2.4GHz low power wireless transceiver analog front-end for the endoscopy capsule system in 0.25/spl mu/m CMOS process. The prototype integrates a low-IF receiver analog front-end (low noise amplifier, double balanced down-converter, band-pass filtered AGC loop and ASK detector) and a direct up-conversion transmitter analog front-end (20MHz IF PLL with well defined amplitude control circuit, ASK modulator, up-converter and output buffer) on a single chip together with an internal RF local oscillator and LO buffers. Design trade-offs have been made over the boundaries of the different building blocks to optimize the overall system performance. All building blocks feature circuit topologies that enable comfortable operation at low power consumption. As a result, the IC operates from a power supply of 2.5 V, while only consuming 15mW in receiver (RX) mode and 14mW in transmitter (TX) mode.

A fifth-order elliptic low-pass Gm-C filter used in monolithic DAB receiver is presented, the filter integrates an on-chip frequency automatic tuning circuit based on PLL to control the cutoff frequency. The filter has been implemented in 0.25/spl mu/um CMOS process. The measurement results show that the frequency tuning error is within 1%, the dynamic range is 54dB, the stop-band rejection rate is greater than 40dB. The filter draws 13mA current from a 3.3V power supply.

This paper presents a fully integrated CMOS low-IF receiver working at L-band for DAB application. An image-rejection low noise amplifier (LNA) supplies over 30dB image rejection in the whole band. A calibration circuit improves matching of quadrature LO signals. Together with the quadrature weaver architecture, the receiver rejects the image signal more than 65dB. The receiver's noise figure is 4dB and OIP3 is 22dBm. The receiver is implemented in 0.25um CMOS process. The core die area is 9mm2.

By analysing the principle of multi-thresholded neurons (MTNs), a methodology is developed for designing multi-thresholded neuron circuits (MTNCs). First, two n-channel MOS transistors are employed to design the voltage-mode synapse circuit with high simplicity and linearity. Second, a BiCMOS technique based circuit named judgement-converting switch (JCS) is proposed. The JCS whose threshold is voltage-controlled current signal, provides an ability of converting the voltage signal to current signal. Based on this possibility, an approach is put forward to design multi-thresholded judgement function circuits (MTJFCs). Finally, single MTNC is designed for implementing XOR operation at switch level. Simulation results with PSPICE show that the designed circuits not only have the correct logic function but also small propagation delay.