We present a two-dimensional layout compactor with octagonal geometry.We discuss layout optimization algorithms used within a topological framework.We present the results of comparing the compactor against a standard set of benchmarks.This version of the compactor uses an iterative greedy layout optimization algorithm with wire minimization and produces leafcells more compact than others published.

An effective approach to two-dimensional compaction of VLSI circuit layouts is discussed. Active devices are described in terms of circular primitives called bubbles. The wires are treated topologically in that no geometric representation is used for them during compaction. This avoids expensive geometrical manipulations of the wires. Cells are compacted by moving bubbles one at a time along design rule preserving paths so as to minimize a cost function directly related to the size of the cell. Geometrical realizations of the wires are reconstructed at the end of the compaction process. The resulting routing has minimum wire length for each wire.>