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Chenghuai Lu

dblp:92/1895 · DBLP profile ↗
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7ranked-venue papers
2as first author
0since 2021 · last 2006
—ORCID · none

Domains — the database's venue-derived domains; a paper can count in several

Systems, architecture and hardware · 3 · 1 first-authorSecurity and privacy · 3Computer networks · 1 · 1 first-authorSoftware engineering, systems software and programming languages · 1

Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.

Network and information security
1 paper
Hardware security and side channels · 100%
Computer architecture, parallel and distributed computing, and storage systems
1 paper
Memory systems · 100%

Topics — the 3 heaviest of 3, each with the papers that count most for it

TopicWeightPapersLastEvidence papers
Hardware security and side channels › memory encryption
counter mode encryption
0.112005
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation · ISCA 2005
Hardware security and side channels
memory encryption
0.112005
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation · ISCA 2005
Memory systems › memory access latency
cache access latency
0.012005
High Efficiency Counter Mode Security Architecture via Prediction and Precomputation · ISCA 2005

Methods — techniques the papers use, named apart from their topics

sequence number prediction · 0.1precomputation · 0.1adaptive prediction · 0.1
YearPublicationVenuePosition
2006 M-TREE: A high efficiency security architecture for protecting integrity and privacy of software
Chenghuai Lu, Tao Zhang 0037, Hsien-Hsin S. Lee
J. Parallel Distributed Comput.1
2005 Memory-Centric Security Architecture
Chenghuai Lu, Hsien-Hsin S. Lee
HiPEAC2
2005 High Efficiency Counter Mode Security Architecture via Prediction and Precomputation
abstract
Encrypting data in unprotected memory has gained much interest lately for digital rights protection and security reasons. Counter mode is a well-known encryption scheme. It is a symmetric-key encryption scheme based on any block cipher, e.g. AES. The scheme's encryption algorithm uses a block cipher, a secret key and a counter (or a sequence number) to generate an encryption pad which is XORed with the data stored in memory. Like other memory encryption schemes, this method suffers from the inherent latency of decrypting encrypted data when loading them into the on-chip cache. In this paper, we present a novel technique to hide the latency overhead of decrypting counter mode encrypted memory by predicting the sequence number and pre-computing the encryption pad that we call one-time-pad or OTP. In contrast to the prior techniques of sequence number caching, our mechanism solves the latency issue by using idle decryption engine cycles to speculatively predict and pre-compute OTPs before the corresponding sequence number is loaded. This technique incurs very little area overhead. In addition, a novel adaptive OTP prediction technique is also presented to further improve our regular OTP prediction and precomputation mechanism. This adaptive scheme is not only able to predict encryption pads associated with static and infrequently updated cache lines but also those frequently updated ones as well. Experimental results using SPEC2000 benchmark show an 82% prediction rate. Moreover, we also explore several optimization techniques for improving the prediction accuracy. Two specific techniques, two-level prediction and context-based prediction are presented and evaluated.
Hsien-Hsin S. Lee, Mrinmoy Ghosh, Chenghuai Lu, Alexandra Boldyreva
ISCA4
2005 A note on efficient implementation of prime generation algorithms in small portable devices
Chenghuai Lu, André L. M. dos Santos
Comput. Networks1
2004 Attacks and risk analysis for hardware supported software copy protection systems
abstract
Recently, there is a growing interest in the research community to use tamper-resistant processors for software copy protection. Many of these tamper-resistant systems rely on a specially tailored secure processor to prevent, 1) illegal software duplication, 2) unauthorized software modification, and 3)unauthorized software reverse engineering. The published techniques primarily focused on feasibility demonstration and design details rather than analyzing security risks and potential attacks from an adversary's perspective. The uniqueness of software copy protection may lead to some potential attacks on such a secure environment that have been largely ignored or insufficiently addressed in the literature. One should not take security for granted just because it is implemented on a tamper-resistant secure processor. Detailed analysis on some proposed ideas reveal potential vulnerability and attacks. Some of the attacks are known to the security community, nevertheless, their implications to software copy protection are not well understood and discussed. This paper presents these cases for designers to improve their systems and circumvent the potential security pitfalls and for users of such systems to be aware of the potential risks
Hsien-Hsin S. Lee, Chenghuai Lu, Tao Zhang 0037
Digital Rights Management Workshop3
2003 Malicious ICMP Tunneling: Defense against the Vulnerability
Ola Nordström, Chenghuai Lu, André L. M. dos Santos
ACISP3
2002 Protecting Web Usage of Credit Cards Using One-Time Pad Cookie Encryption
abstract
The blooming e-commerce is demanding better methods to protect online users' privacy, especially the credit card information that is widely used in online shopping. Holding all these data in a central database of the Web sites would attract hackers' attacks, impose unnecessary liability on the merchant Web sites, and raise the customers' privacy concerns. We introduce and discuss in detail the secure distributed storage of sensitive information using HTTP cookie encryption. We are able to employ One-Time Pads to encrypt the cookies, because encryption and decryption are both done by the server, which is an interesting characteristic overlooked by the existing systems. We implemented this protocol and showed that it is simple, fast and easy to program with.
Donghua Xu, Chenghuai Lu, André L. M. dos Santos
ACSAC2