EDBT 2026 Demo / reviewers in the wild / expert
Karol Kalna
dblp:92/2410
· DBLP profile ↗
1ranked-venue papers
0as first author
0since 2021 · last 2011
0000-0002-6333-9189ORCID · verified
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 1
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
1 paper |
Electronic design automation · 50% Integrated circuit design · 50% |
Topics — the 1 heaviest of 2, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation › technology computer-aided design
device simulation |
0.1 | 1 | 2011 | Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled Transistors · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2011 |
Methods — techniques the papers use, named apart from their topics
finite element method · 0.1finite difference method · 0.1drift-diffusion simulation · 0.1density-gradient approach · 0.1
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2011 | Implementation of the Density Gradient Quantum Corrections for 3-D Simulations of Multigate Nanoscaled TransistorsabstractAn efficient implementation of the density-gradient (DG) approach for the finite element and finite difference methods and its application in drift-diffusion (D-D) simulations is described in detail. The new, second-order differential (SOD) scheme is compatible with relatively coarse grids even for large density variations thus applicable to device simulations with complex 3-D geometries. Test simulations of a 1-D metal-oxide semiconductor diode demonstrate that the DG approach discretized using our SOD scheme can be accurately calibrated against Schrödinger-Poisson calculations exhibiting lower discretization error than the previous schemes when using coarse grids and the same results for very fine meshes. 3-D test D-D simulations using the finite element method are performed on two devices: a 10 nm gate length double gate metal-oxide-semiconductor field-effect transistor (MOSFET) and a 40 nm gate length Tri-Gate fin field-effect transistor (FinFET). In 3-D D-D simulations, the SOD scheme is able to converge to physical solutions at high voltages even if the previous schemes fail when using the same mesh and equivalent conditions. The quantum corrected D-D simulations using the SOD scheme also converge with an atomistic mesh used for the 10 nm double gate MOSFET saving computational resources and can be accurately calibrated against the results from non-equilibrium Green's functions approach. Finally, the simulated ID-VGcharacteristics for the 40 nm gate length Tri-Gate are in an excellent agreement with experimental data. Antonio J. García-Loureiro, Natalia Seoane, Manuel Aldegunde, Raúl Valín Ferreiro, A. Asenov, Antonio Martinez, Karol Kalna |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 7 |