In this paper, we base on data computing blocks (DCBs) and DCT watchdog technology to implement VLIW watchdog processor. 32-bit final DCT signature (F-DCT-S) and several 5-bit relay DCT signatures (R-DCT-S) will be computed by DCT watchdog scheme. These generated signatures are embedded into the instruction memory and then used to do the run time error checking. We use VLIW processor to simulation. In this paper, the processor degradation can be improved by doing the whole block error checking after the branch instruction, the fault detection latency is improved by doing the intermediate error checking at the R-type instruction, and the memory overhead is reduced by storing the R-DCT-S to the R-type instruction. The experimental results show that the proposed watchdog has a very high error detection coverage and shortest error detection latency to detect either single fault or multi-faults, no matter what the fault is transient or intermittent.

In this paper, we present a new concurrent error-detection scheme by hybrid signature to the online detection of program memory and control flow errors caused by transient and intermittent faults. The proposed hybrid signature-monitoring technique combines the vertical signature with the horizontal signature schemes. We first develop a new vertical signature based on linear additive code whose signature length could be easily adjusted. The attribute of adjustable length in vertical signature offers the feasibility to integrate the vertical signature, horizontal signature, and length of block into a single signature word. The horizontal signature mechanism can compensate for the coverage degradation due to the reduction of vertical signature length and significantly decrease the error-detection latency as well. The extensive block-based bit-error simulation and hardware-based simulated fault injection experiment are conducted to validate the effectiveness of the proposed technique: compared to the continuous signature monitoring (CSM) scheme, there are several notable enhancements accomplished in our work. One is the fault model used in our work is more realistic than the model employed in CSM. Another is the hardware-based experiments are performed so as to measure the design parameters more accurately. The final one is our scheme does not require being equipped with SEC-DED code in program memory in order to achieve the horizontal signatures if instruction bit correction is not an essential demand; as a result, our scheme is more flexible than CSM.

This paper presents an effective reconfiguration scheme consisting of detailed spare replacement, processor placement, routing, and switch programming mechanisms. A new switch programming scheme is proposed to reduce the hardware overhead of reconfiguration. A thorough yield simulation tool has been developed for accurate prediction of yield by considering the effects of defect clusters and switching network failures. This yield simulation tool can also be used to obtain the information on the performance degradation, spare replacement, processor placement, routing and the switch programming algorithm survival probability.

A class of fault-tolerant Very Large Scale Integration (VLSI) and Wafer Scale Integration (WSI) schemes, called the multiple-level redundancy, which incorporates both hierarchical and element level redundancy has been proposed for the design of high yield and high reliability large area array processors. The residual redundancy left unused after successfully reconfiguring and eliminating the manufacturing defects can be used to improve the operational reliability of a system. Since existing techniques for the analysis of the effect of residual redundancy on reliability improvement are not applicable, we present a new hierarchical model to estimate the reliability of the systems designed by our approach. Our model emphasizes the effect of support circuit (interconnection) failures on system reliability, leading to more accurate analysis. We discuss two area prediction models, one based on the regular WSI process, another based on the advanced WSI process, to estimate the area-related parameters. This analysis gives an insight into the practical implementations of fault-tolerant schemes in VLSI/WSI technology. Results of a computer experiment conducted to validate our models are also discussed.>

The locally redundant modular tree (LRMT) schemes offer high yield and reliability for trees of relatively few levels but are less effective for large binary trees due to the imbalance of reliability of different levels. A new multiple-level redundancy tree (MLRT) architecture that combines modular schemes with level-oriented schemes which lead to better yield and reliability is presented. The MLRT structure enhances the wafer yield to significant levels by offering separate layers of protection for random and clustered defects. Unlike most existing techniques, this technique performs a more accurate reliability analysis by taking into account both switch and link failures. A measure called the marginal switch to processing element area ratio (MSR) is introduced to precisely characterize the effect of switch complexity on the reliability of the redundant system. A systematic method for the optimal distribution of spare modules of the MLRT structure is also presented. The analyses show that the MLRT structure offers higher yield and system reliability than LRMT and subtree-oriented fault-tolerance (SOFT) structures do.>

Presents and analyzes a new multiple-level redundancy scheme based on hierarchical and element level redundancy for the enhancement of yield and reliability of large area array processors. This scheme can effectively tolerate not only the random defects/faults, but also the clustered defects/faults. The analysis presented here is general in that it takes into account the chip-kill defects occurring in the support circuit area of the array processors and is applicable to a variety of array processors. The authors derive bounds for the support circuit area which will be useful in selecting the most cost-effective redundancy scheme for a given application. The concept of subprocessing element-level redundancy is discussed and it is shown that a combination of subprocessing element-level redundancy with hierarchical redundancy offers significant yield improvements, especially for array processors with large area processing elements. The problem of optimal redundancy is also addressed.>