As VLSI silicon technology continues its relentless advance and memory densities increase, the problem of soft errors--bit upsets caused by alpha particles or neutron hits--demands solutions. Error-correcting codes (ECCs) are routinely used on random-access memories (RAMs) to increase soft error tolerance--codewords (CWs) (ECC bits concatenated to the data) are written to and read from memory, and the read CW is decoded to correct errors. Content addressable memories (CAMs) also demand error mitigation measures. The method employed for RAMs is also applicable to CAMs: the match-line sense amplifier is modified to function as a comparator [1], CWs are stored and searched for. We investigate the extension of this method to ternary CAMs (TCAMs). TCAMs cannot employ the efficient ECCs (known as linear block codes-LBCs) used with RAMs and CAMs. We develop the ECCs necessary to implement error-resilient TCAMs. We prove that the rate (ratio of data bits to total number of bits in the CW) of the specialized ECCs necessary for TCAMs cannot exceed 1/t, where t is the number of bit errors the code can correct (in contrast, LBCs asymptotically have rate one); simple majority codes are the best.

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Hardware systems are generally specified as a set of interacting finite state machines (FSMs). An important problem in formal verification using Binary Decision Diagrams (BDDs) is forming the transition relation of the product machine. This problem reduces to conjuncting (or multiplying) the BDDs representing the transition relations of the individual machines, and then existentially quantifying out the set of input and output variables. The resulting graph is called the product graph. Computing the set of reachable states of the product graph is the central verification problem. In this paper, we discuss two related problems. The early quantification problem is the problem of interleaving multiplication of a set of BDDs with the quantification of a set of variables so that the size of the largest BDD encountered is minimized. We show that an abstraction of this problem is NP-complete, and provide heuristic solutions for it. In some cases, the size of the BDD representing the transition relation of the product graph is too large. The partitioned transition relations problem deals with partially combining the BDD's and quantifying as many variables as possible, so that the time for computing the set of reachable states of the product graph is minimized. We offer heuristic solutions to this problem based on our algorithms for early quantification. The algorithms have been implemented and good experimental results have been achieved.

Article Free Access Share on HSIS: a BDD-based environment for formal verification Authors: A. Aziz Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , F. Balarin Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , S.-T. Cheng Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , R. Hojati Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , T. Kam Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , S. C. Krishnan Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , R. K. Ranjan Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , T. R. Shiple Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , V. Singhal Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , S. Tasiran Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , H.-Y. Wang Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , R. K. Brayton Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile , A. L. Sangiovanni-Vincentelli Department of EECS, University of California at Berkeley, Berkeley, CA Department of EECS, University of California at Berkeley, Berkeley, CAView Profile Authors Info & Claims DAC '94: Proceedings of the 31st annual Design Automation ConferenceJune 1994 Pages 454–459https://doi.org/10.1145/196244.196467Published:06 June 1994Publication History 39citation325DownloadsMetricsTotal Citations39Total Downloads325Last 12 Months36Last 6 weeks17 Get Citation AlertsNew Citation Alert added!This alert has been successfully added and will be sent to:You will be notified whenever a record that you have chosen has been cited.To manage your alert preferences, click on the button below.Manage my AlertsNew Citation Alert!Please log in to your account Save to BinderSave to BinderCreate a New BinderNameCancelCreateExport CitationPublisher SiteeReaderPDF