Digital-to-time converter (DTC) or digital delay/timing generator has been developed for quite many years and plays a crucial role in automatic test equipment (ATE) and built-in self-test (BIST) industries. This study proposes a compact multidimensional delay array DTC based on phase shift in a phase-locked loop (PLL) to further extend field-programmable gate array (FPGA) applications into the analog domain. All internal delay cells are precisely controlled by PLL from the beginning to make the output phases distributed within the reference clock period as uniformly as possible. For further resolution enhancement, a hybrid structure based on PLL and a multidimensional delay array is presented to ensure high enough accuracy and substantially reduce logic utilization through phase sorting and selection. For concept proving, the proposed four-channel DTC is implemented on an Altera Stratix IV FPGA board to achieve 20 internal control bits, 2-ps resolution with very low integral nonlinearity (INL) and differential nonlinearity (DNL) of −2.06 to 2.01 and −2.50 to 2.31 LSB, respectively. In addition, the circuit has been successfully implemented on a much cheaper Cyclone IV platform also for cost reduction to achieve the same resolution with the best fine stage INL and DNL of −3.81 to 3.56 and −3.93 to 4.41 LSB, respectively. The DTC performance has demonstrated improvements to that of prior arts by one order finer resolution and higher accuracy compared to non-Vernier prior works, while eliminating the serious dead time issues inherent in Vernier DTCs.

This article presents an ultrasmall area on-chip relaxation oscillator with low-temperature sensitivity. In this design, a virtual resistor mainly composed of a complementary to absolute temperature (CTAT) voltage reference circuit is implemented to replace the real resistor for efficient temperature compensation, which counterbalances the inherent proportional to absolute temperature (PTAT) property of the original relaxation circuit of the oscillator. The conventional capacitor is also replaced with a MOS capacitor to complete the ALL-MOS oscillator circuit with two prime advantages, one of which is larger capacitance to area density, and the other is better matching with critical MOSFETs. Implemented in a 0.18-$\mu $m TSMC standard CMOS process, the proposed relaxation oscillator has achieved a temperature coefficient of 28.17 ppm/°C over the temperature range from$- 25~^{\circ }$C to$+ 125~^{\circ }$C at 11.39-MHz oscillation frequency. This circuit consumes$243.1~\mu $W under 1.3-V power supply. Along with the abovementioned excellent performance, the oscillator achieves an ultrasmall core chip area of 0.009 mm2, which is almost one order less than most of the prior arts’ in the same process.

A$216\times216$under-display optical fingerprint CMOS image sensor (CIS) is proposed and was prototyped using 0.11-$\mu \text{m}$CIS technology. Two analog storage nodes that act as a ping-pong buffer are embedded in each pixel of the global-shutter CIS, rendering a digital buffer unnecessary and increasing the operating frame rate. A processor with automatic exposure (AE) and black-level correction is embedded in the CIS to shorten the data transmission time. The AE and dynamic range enhancement functions are initiated to increase the success rate of fingerprint recognition. The full well capacity and sensitivity of the global-shutter CIS are 9 ke− and 21 V/(lux$\cdot $s), respectively. A prototype of the fingerprint sensor consumed only 26 mW with a 3.3-V supply voltage. An imaging lens and the CIS were combined to form the prototype of a compact camera module (CCM). Each pixel size is$6.8\times 6.8\,\,\mu \text{m}^{2}$, equivalent to a panel resolution of 747 dots per inch with an optical ratio of 5. The sensor chip size is$2.23\times2.39$mm2, and the sensing area is$1.469\times1.469$mm2, occupying 40.5% of the chip. The prototype CCM was successfully embedded in a mobile phone, and the performance of the CIS was validated in the temperature range of −20°C to 50°C. Even when the interrupt interval for the serial peripheral interface communication was 300 ms, the CIS as a slave device could capture the fingerprint images clearly.

A low flicker dimmable four-channel LED driver with precise current balancing is proposed in this paper. It is able to achieve highly linear dimming and low lighting flicker at the same time by utilizing a new matrix-style digital pulsewidth modulation (DPWM) along with LED string rotation. Only one LED string needs to be modulated to reduce the total LED current variation and switching loss. To avoid color shift and reduce the effect of subharmonic flicker, a fourth-order common centroid layout is applied to match the current-controlling MOSFETs for precise current balancing. Low-voltage and high-temperature protection circuits as well as a temperature-compensated relaxation oscillator are all integrated to complete the driver design and reduce the overall cost for practical applications. The chip is designed in a TSMC 0.25-μm 1P3M 60-V high-voltage CMOS process with a chip size of 1.76 × 1.37 mm2. The current mismatch among LED strings is measured to be only ±0.28% along with four times reduction in lighting flicker.

An extremely high-resolution, 2-D Vernier field-programmable gate array (FPGA) time-to-digital converter (TDC) with phase wrapping and averaging has been proposed recently to get an extremely fine resolution of 2.5 ps. However, the cell delays in a delay matrix are not fully controlled so that the TDC performance strongly depends on the stochastic distribution of cell delays, and the input range is limited to less than 20 ns. To achieve both high-precision phase division and wide measurement range, a phase-locked loop (PLL)-based delay matrix, which is capable of overclocking and double data rate (DDR), is proposed in this article. All delay cells are under the precise control of PLLs to generate output phases evenly divided within the reference clock period. For a concept proof, the TDC architecture is implemented on an Altera Stratix-IV FPGA chip to achieve 15.6-ps resolution. The differential nonlinearity (DNL), integral nonlinearity (INL), and rms resolution are measured to be merely -0.157 to 0.137 LSB, -0.176 to 0.184 LSB, and 1.0 LSB, which prove the superiority of the proposed structure to its stochastic counterparts. The proposed high-precision phase division technique can be applied to not only the TDC but also the digital-to-time converter (DTC) to enrich its future applications.

While on-chip delay measurement combining logic BIST with a variable test clock is an effective way to secure field reliability of VLSI/FPGAs, validation of the variable test clock generated on the chip is important to guarantee measurement accuracy. This paper addresses a method of on-chip test clock validation using a TDC (Time-to-Digital Converter) for FPGAs. The proposed method has two operation modes, one is a resolution measurement mode and the other is a phase difference measurement mode. The resolution measurement mode is performed first to check the resolution of the TDC circuit. The phase difference measurement mode checks the timing difference between the original clock and the generated test clock. Evaluation experiments using a real FPGA device shows that the resolution of the proposed clock validation method using a TDC is 50.46 ps. For a variable test clock with resolution of 96.15 ps, it was confirmed that INL (Integral Non-Linearity) of the clock is within 10% and it was inconsistent with a result observed by an oscilloscope.

I. VLSI Systems: A Glance Into The Last Decades Since their inception in 1970s, VLSI systems have enabled several new technological capabilities and made them accessible to an unceasingly wider range of users, reaching a scale that has been exponentially increasing over the decades[1](seeFig. 1). Relentless integration of more complex systems has driven such remarkable evolution, as made possible by the inexorable miniaturization. As shown inFig. 1, more functionality has been crammed in a consistently smaller form factor, as exemplified by the physical volume shrinking of computers by 100 X/decade[2],[3]. At the same time, the energy per task has been decreasing at 10–100 X/decade, as shown inFig. 2, for several systems and system-on-chip subsystems[4]. This allowed packing more capabilities into the same power envelope, as generally observed in the electronic systems, even before the advent of the integrated circuit[5].

Mismatches caused by random and systematic variations among identical designed devices usually dominate the performance of analog circuits, where the former can be controlled by increasing area, while the latter should be tackled by careful layout design. Most of existing studies propose analog placement methodologies with the common centroid constraint to mitigate the linear systematic gradient effect. However, nonlinear gradient error compensation should also be addressed for circuits requiring high performance. This paper presents a current source placement algorithm considering quadratic (second order) gradient error for a high-accuracy current-steering digital-to-analog converter to pursue excellent linearity. A new switching scheme and a submatrix swapping technique are proposed to maximize quadratic gradient compensation, and a simulated annealing-based matrix perturbation algorithm is also proposed to directly minimize integral nonlinearity (INL). In addition, to tackle the extremely high complexity of current source interconnections, we model the routing instance as a branch assignment problem and propose an optimal greedy-based algorithm, which is inspired by the well-known left-edge algorithm. The experimental results show an order of magnitude reduction in INL compared to a state-of-the-art nonlinear gradient-aware current source placement approach and better dynamic performance in post-layout simulation.

As I start my second two-year term (2017–2018) as the Editor-in-Chief (EIC) of the IEEE Transactions on Very Large Scale Integration Systems (TVLSI), I wish the TVLSI readership a very happy new year and continued professional success. It gives me great pleasure to report on the state of the journal and our performance metrics. Over the past two years, TVLSI has seen a healthy increase in the number of submissions—from 687 in 2014 to 770 in 2015, and at the time of writing of this editorial, we are at 760 submissions for 2016. We expect the number of submissions for 2016 to cross 800 before the end of the year. TVLSI, therefore, continues to be the premier archival journal for university researchers and industry practitioners in the broad area of VLSI system design.

A high-resolution time-to-digital converter (TDC) implemented with field programmable gate array (FPGA) based on delay wrapping and averaging is presented. The fundamental idea is to pass a single clock through a series of delay elements to generate multiple reference clocks with different phases for input time quantization. Due to periodicity, those phases will be equivalently wrapped within one reference clock period to achieve the required fine resolution. In practice, a hybrid delay matrix is created to significantly reduce the required number of delay cells. Multiple TDC cores are constructed for parallel measurements and then exquisite routing control and averaging are applied to smooth out the large quantization errors caused by the inhomogeneity of the TDC delay lines for both linearity and single-shot precision enhancement. To reduce the impact of temperature sensitivity, a cancellation circuit is created to substantially reduce the offset and confine the output difference within 2 LSB for the same input interval over the full operation temperature range of FPGA. With such a fine resolution of 2.5 ps, the integral nonlinearity is measured to be from merely -2.98 to 3.23 LSB and the corresponding rms resolution is 4.99-6.72 ps. The proposed TDC is tested to be fully functional over 0 °C-50 °C ambient temperature range with extremely low resolution variation. Its performance is even superior to many full-custom-designed TDCs.

This paper presents the first voltage-calibrated CMOS time-domain smart temperature sensor to reduce the cost of mass production. A digitally adjustable relaxation oscillator designed as the temperature sensor vibrates between CMOS-based CTAT, PTAT voltage references with mutual curvature compensation to generate linear temperature-dependent output pulses. Voltage instead of temperature calibration is adopted to alleviate the impact of process variation and TDC is used for output coding. Fabricated in a TSMC 0.18-μm standard CMOS process, the proposed sensor is able to operate at a high speed of 486k samples/sec for SoC thermal monitoring. The active area is merely 0.122 mm2and the inaccuracy is measured to be less than ±1°C for 15 test chips in a wide temperature range of -40°C to 120°C. The performance is even superior to some chips with one- or two-point temperature calibrations. A milestone is established for time-domain smart temperature sensor to get rid of the heavy burden of fixed-temperature calibration with reason error budget.

The protocol allows a 1.0 transmission probability for newly transmitted packets, while p for retransmitted packets. Compared to the protocol in which each packet is always transmitted with the same probability p, it shows better performance, especially when the channel traffic is light, as demonstrated by numerical results.>