Many Software (SW) vendors limit the functionality of their product based on the version purchased. This trend has also carried over to Electronic Design Automation (EDA). For example, Field-Programmable Gate Array (FPGA) vendors make their Lite versions freely available to anyone, but charge for their full versions, e.g., Intel Quartus Prime Lite vs. Quartus Prime. Some High-Level Synthesis (HLS) tool vendors have started to do the same in order to appeal more to FPGA users who are more price conscious as opposed to the ASIC users. FPGA tools are typically free or very inexpensive and hence, it makes sense to have dedicated FPGA versions of their HLS tools. To enable this strategy some HLS vendors have put in place different control mechanisms to avoid anyone using their inexpensive FPGA version to target ASICs, as this would defeat their price discrimination strategy. In this work, we review different strategies used by the HLS vendors and propose to the best of our knowledge the first technique to circumvent these. For this we leverage the inherent modularity of software tools to circumvent the locks. In particular we show how we can generate ASIC circuits with similar area and performance using the Lite HLS version that only allows to target small FPGAs as compared to using the full ASIC HLS version 1 .

This work introduces a complete flow to make legacy, side-channel attack (SCA) unaware, hardware given as an Register Transfer Level (RTL) description (Verilog) secure through an RTL to C compiler that generates optimized C code for High-Level Synthesis (HLS). This compiler analyzes the legacy RTL description against SCA and generates C code that can then be in turn re-synthesized into new RTL code that is security-aware. Experimental results show that our proposed flow is able to make security unaware RTL code secure introducing minimal overheads.

This work introduces a secure split logic synthesis (cloud+local) approach to enable Third Party Intellectual Property (3PIP) vendors that do not have access to expensive state-of-the-art logic synthesis tools to efficiently and securely synthesize their IPs with minimal area and delay overheads. For this, we propose to split the Register Transfer Level (RTL) IP given in Verilog or VHDL such that one part is synthesized on the cloud using a state-of-the-art commercial logic synthesis tool (e.g., Synopsys Design Compiler) while synthesizing locally, on the IP vendor's side, the missing portion of the design using free logic synthesis tools (e.g., Yosys). This approach allows 3PIPs to leverage the power of commercial logic synthesis tools while protecting their IP from anyone having access to the cloud where the logic synthesis tools is hosted without fearing that the IP will be stolen. Experimental results show that our proposed flow is secure, while leading to negligible area and delay overheads. In particular, the proposed flow has an average area overhead of 0.94% to 1.81% for different types of design implementations and in all cases the original timing constraint is met.

This work introduces a novel computer architecture consisting of an embedded processor with a tightly coupled Coarse-grain Re-configurable Array (CGRA) that is able to accelerate the execution of sequential programs at runtime. To accomplish this, our work pre-characterizes a large variety of different portions of code from multiple application domains that can be accelerated offline. These kernels are subsequently synthesized onto the CGRA such that the proposed architecture detects at runtime if portions of code from a new unseen application can be accelerated or not at runtime. If they can be accelerated, then the system autonomously configures the CGRA with the specific accelerator, while if not present, then the code is executed sequentially on the CPU only. This approach implies sequential code compiled for a specific CPU only does not need to be recompiled for alternative architectures like CPU+CGRA.

Approximate computing is a relatively new computing paradigm that allows to trade-off area/power with accuracy. Another relatively new VLSI design trend is to raise the level of design abstraction from the Register-Transfer Level (RTL) to the behavioral level and use High-Level Synthesis (HLS) to synthesize these behavioral descriptions. HLS has one unique advantage over RTL design. It completely decouples the functional description from the implementation details. This allows to design and verify the behavioral description once, but then generate a large number of functional equivalent hardware implementations of unique area vs. performance trade-offs. This is typically achieved through synthesis directives in the form of pragmas that the HLS user annotates at the source code to mainly control how to synthesize arrays (RAM, registers), loops (unroll, pipeline) and functions (inline or not).In this work we leverage this uniqueness and build an automated HLS design space explorer to find the hardware circuit most amenable to approximate computing, this is, has the highest potential for area/power savings. We have coined this explorer ADVISOR. The main problem with traditional exploration approaches is their long run time, which is worse in this case because every new implementation needs to be approximated to fully understand the trade-offs in terms of area/power vs. error. Thus, in order to accelerate this exploration process, we propose to evaluate each new designs based on an Approximation Friendliness Index (AFI) that can be computed statically, very fast, and only fully approximate the designs recommended by our flow that have high AFI values. Experimental results show that this approach leads to basically the same results as exhaustively approximating every new design, while being on average 68 × faster.

Most VLSI design companies are now fabless. This forces them to rely on complex international supply chains that can compromise their Intellectual Property (IP). One popular approach to address this is through logic locking [1], [2]. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the (HW) design company delivers to the foundry, which has now access to the entire design, including the locking mechanism [3]. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. An alternative approach is to redact a portion of the hardware design by mapping it to an embedded FPGA (eFPGA). The unprogrammed design is then sent to be fabricated at an untrusted fab, which can now not reverse engineer the design because they do not have the bitstream configuration that makes the entire chip operate correctly. The bitstream acts in this case as the locking key. Hardware redaction is nevertheless not 100% secure, and different attacks have already been proposed [4]. The main problem with most of these attacks is that they require long simulation times, but in reality, when applied to the actual hardware, are executed much faster. Thus, in this work, we propose an open-source FPGA-based hardware redaction framework to speed up new attacks with the ultimate goal of learning how to build more robust hardware redaction systems. The framework is composed of an automated ASIC and FPGA partitioning tool, the mapping of these parts onto a low-cost FPGA board (Terasic DE10-SoC[5]) and a library of software APIs that run on the embedded processor of the FPGA in order to launch attacks onto the redacted systems mapped onto the FPGA fabric. The experimental results show that the emulation platform is orders of magnitude faster than a pure simulation-based approach while also scaling much better. The entire platform is available online at https://github.com/chaitalisathe/FREEDOM.

Designing hardware at the register transfer level (RTL) using low-level hardware description languages (HDLs) like Verilog or VHDL gives designers large degrees of controllability to create hardware architectures that will meet the given cost, power budget and performance requirements. The main problem with this approach is that the manually optimized architecture is fixed, which implies that future redesigns to, e.g., target other hardware platforms like field-programmable gate arrays (FPGAs) or newer technologies nodes might require the redesign and reverification of the RTL description. This is error prone and time consuming. To address this, in this work, we propose an RTL to C compiler that generates C code optimized for high-level synthesis (HLS) such that the redesign and reoptimization of new hardware design can be automated. HLS has multiple significant advantages over traditional RT-level design flows like being able to design and verify the behavioral description once and then retarget it for different hardware platforms and constraints by simply using a new technology library and synthesis constraints. Moreover, HLS allows to generate multiple functional equivalent design variants with unique tradeoffs like area, performance, and power from the same behavioral description by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers) and loops (unroll, partially unroll, no unroll, or pipeline). In order to leverage these advantages, in this work, we introduce an RTL to C compiler framework that we call MIRROR: maximizing the reusability of RTL through RTL to C Compiler and its new improved version MIRROR++ that is able to compile back to C different types of RTL descriptions, including pipelined circuits, finite state machines, and circuits that share functional units generating arrays and loops so that these can in turn be resynthesized (HLS) with different synthesis directives. Experimental results show the effectiveness and robustness of our approach.

Most Register Transfer Level (RTL) designs originate from behavioral descriptions specified in C or C++ often written by Software (SW) designers. Hardware (HW) designers then manually describe an efficient hardware implementation of that application using a Hardware Description Language (HDL) like Verilog or VHDL. Although it has been shown that High-Level Synthesis (HLS) provides a direct path to synthesizing these behavioral descriptions into RTL, the quality of the generated RTL is often still unacceptable, hence, requiring to manually design the HW. This is nevertheless time consuming and error prone. In particular, finding bugs introduced in the manual design is very tedious as HW designers rely on long simulations that generate large waveforms that have to be thoroughly scrutinized.

Many Software (SW) vendors limit the functionality of their product based on the version purchased. This trend has also carried over to Electronic Design Automation (EDA). For example, Field-Programmable Gate Array (FPGA) vendors make their Lite versions freely available to anyone, but charge for their full versions, e.g., Intel Quartus Prime Lite vs. Quartus Prime. Some High-Level Synthesis (HLS) tool vendors have started to do the same in order to appeal more to FPGA users who are more price conscious as opposed to the ASIC users. FPGA tools are typically free or very inexpensive and hence, it makes sense to have dedicated FPGA versions of their HLS tools. To enable this strategy some HLS vendors have put in place different control mechanisms to avoid anyone using their inexpensive FPGA version to target ASICs, as this would defeat their price discrimination strategy.

One approach that has been suggested to further reduce the energy consumption of heterogenous Systems-on-Chip (SoCs) is approximate computing. In approximate computing the error at the output is relaxed in order to simplify the hardware and thus, achieve lower power. Fortunately, most of the hardware accelerators in these SoCs are also amenable to approximate computing.

This work presents a RTL to C compiler called MIRROR that maximizes the re-usability of the generated C code for High-Level Synthesis (HLS). The uniqueness of the compiler is that it generates C code by using libraries of pre-characterized RTL micro-structures that are uniquely identifiable through perceptual hashes. This allows to quickly generate C descriptions that include arrays and loops. These are important because HLS tools extensively use synthesis directives in the form of pragmas to control how to synthesize these constructs. E.g., arrays can be synthesized as registers or RAM, and loops fully unrolled, partially unrolled, not unrolled, or pipelined. Setting different pragma combinations lead to designs with unique area vs. performance and power trade-offs. Based on this, the main goal of our compiler is to parse synthesizable RTL descriptions specified in Verilog which have a fixed micro-architecture with specific area, performance and power profile and generate C code for HLS that can then be re-synthesized with different pragma combinations generating a variety of new micro-architectures with different area vs. performance trade-offs. We call this 'maximizing the re-usability of the RTL code because it enables a path to re-target any legacy RTL description to applications with different constraints. In particular we deal with pipelined descriptions in this work due to their uniqueness. Experimental results show that our proposed compiler is very effective, opening the door to automating the re-optimization of legacy hardware designs previously manually optimized using low level Hardware Description Languages (HDLs). We aim at making this compiler framework open source and available to the research community.

With most hardware (HW) design companies now relying on third parties to fabricate their integrated circuits (ICs) it is imperative to develop methods to protect their Intellectual Property (IP). One popular approach is logic locking. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the (HW) design company delivers to the foundry which has now access to the entire design including the locking mechanism. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. One relatively new approach that has been coined as hardware redaction is to map a portion of the design to an embedded FPGA (eFPGA). The bitstream of the eFPGA now acts as the locking key. In this case the fab receives the design without the bitstream and hence, cannot reverse engineer the functionality of the design. In this work we propose, to the best of our knowledge, the first attack on eFPGA HW redacted ICs by substituting the exact logic mapped onto the eFPGA by a synthesizable predictive model that replicates the behavior of the exact logic. This approach is particularly applicable in the context of approximate computing where hardware accelerators tolerate certain degrees of error at their outputs. One of the main issues addressed in this work is how to generate the training data to generate the synthesizable predictive model. For this we use SAT/SMT solvers as the potential attacker only has access to primary I0 of the IP. Experimental results for various degrees of maximum allowable output errors show that our proposed approach is very effective finding suitable predictive models.

To improve the performance while reducing the power consumption, embedded processors in Systems-on-Chip (SoC) often now include tightly coupled hardware accelerators that can execute dedicated tasks orders of magnitude more efficiently (faster and lower power). These hardware accelerators though require significant hardware resources as one of the main reason for their efficiency is that they extensively exploit the parallelism of these dedicated tasks mapped on them. The question that we address in this work is if these hardware resources can be re-used by the CPU when executing a different application.

Application Specific Instruction Set Processor (ASIPs) have been proposed in the past to increase the performance while reducing the energy of general-purpose processors. These ASIPs are normally generated at the RT-Level (Verilog or VHDL). In this work we leverage the advantages of High-Level Synthesis (HLS) by designing the complete ASIP in ANSI-C. HLS is a single process synthesis method, thus, the key is to merge the CPU and hardware accelerator descriptions. This allows us proposed flow to synthesize the entire system together, which has numerous advantages like being able to reduce the total area, while further minimizing the power as the HLS process can now fully co-optimize the ASIP by e.g., maximizing resource sharing.

High-Level Synthesis (HLS) allows to synthesis un-timed behavioral descriptions into efficient RTL (Verilog or VHDL). Although much progress has been made to improve the quality of HLS it is often reported that the generated RTL code from HLS leads to larger circuits as compared to hand optimized Verilog or VHDL. To measure the gap between hand optimized RTL and automatically generated RTL from HLS, periodic studies are presented were the authors manually optimize designs in RTL, re-write the functionality in C and then compare the quality of the generated RTL code. This is useful, but not very scalable as it is only possible to do this for a small number of designs. Moreover, the result from HLS is highly dependent on the synthesis options used, typically in the case of HLS, these have the form of pragmas (comments) that allow to control how to mainly synthesize arrays (e.g., RAM or registers), loops (e.g., unroll, partially, not unroll) and functions (e.g., inline or not). To address this, in this work we present an RTL to C compiler that generates synthesizable C code for HLS combined with an auto-tuner to automatically find HLS constraints such that the generated RTL code from HLS is as close as possible in terms of area and performance to the original manually optimized RTL code. This allows to directly compare the quality of the generated RTL code by further synthesizing these into equivalent gate netlist.

High-level synthesis (HLS) has multiple significant advantages over traditional RT-level design flows. One in particular that we address in this work is the ability to generate multiple functional equivalent design variants with unique tradeoffs, such as area, performance, and power from the same behavioral description. This is typically done by setting synthesis options in the form or pragmas (comments) to mainly control how to synthesize arrays (RAM or registers), loops (unroll, partially unroll, no unroll or pipeline), and functions (inline or not). Setting different pragma combinations lead to these different design implementations. Out of all the pragma combinations the designer is typically only interested in those that lead to the Pareto-optimal designs (PODs). Fortunately, this search can be automated, but unfortunately, the search space to find these pragma combinations grows supra-linearly with the number of pragma settings. Thus, fast and efficient heuristics are needed. These heuristics generate a new pragma combination and then evaluate their effect by synthesizing (HLS) it. The most time-consuming part of this process is having to execute a full synthesis (HLS) on the behavioral description for every new pragma combination. One obvious way to accelerate the exploration is to parallelize the exploration process using a multithreaded heuristic. The theoretical speedup should match the number of parallel threads. The main problem with this approach is that every HLS invokation requires to check out an HLS tool license. This license is not released until the synthesis process has finished. This implies that the maximum number of parallel threads is restricted by the number of available licenses, which in the ASIC case are extremely expensive. On the contrary, FPGA vendors make their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the PODs in the ASIC case. To address this, in this work we present a dedicated multithreaded parallel HLS design space explorer (DSE) based on transfer learning that is able to accelerate HLS DSE for ASICs by targeting first FPGAs and using machine learning to convert the exploration results obtained to find the optimal ASIC equivalent. Experimental results show the effectiveness and robustness of our approach.

Many applications require simple controllers that continuously run the same application. These applications are often found in battery operated embedded systems that require to be ultra-low power (ULP) and are very price sensitive. Some examples include IoT devices of different nature and medical devices. Currently, these systems rely on off-the-shelf general-purpose microprocessors. One of the problems of using these processors, is that not all of the resources are needed for a specific application. Furthermore, because of the regularity of the workloads running on these systems there is a large opportunity to optimize the processor by pruning those unused resources to achieve lower area (cost) and power. Moreover, these processors can be specified at the behavioral level and use High-Level Synthesis (HLS) to generate an efficient Register Transfer Level (RTL) description. This opens a window to additional optimizations as the processor implementation is fully re-optimized during the HLS process. Also, many applications running on these embedded systems tolerate imprecise outputs. These include image processing and digital signal processing (DSP) applications. This opens the door to further optimizations in the context of approximate computing. To address these issues, this work presents a methodology to customize a behavioral RISC processor automatically for a given workload such that its area and power are significantly reduced as compared to the original, general-purpose processor. First, generating a bespoke processor that leads to the exact output as compared to the original general-purpose one and then by approximating it allowing a certain level of error at the output. Compared to previous work that customizes a given processor at the gate netlist only, our proposed method shows significant benefits. In particular, this work shows that raising the level of abstraction reduces the area and power by 78.3% and 70.1% for the exact solution on average, and further reduces the area by an additional 10.0% and 16.5% for the approximate version tolerating a maximum of 10% and 20% output errors respectively.

This work presents an automated design and optimization flow for near on-chip memory computing systems by placing dedicated hardware accelerators directly next to the onchip memory. The salient feature of our proposed flow is that it allows the design of these complex systems completely at the behavioral level, thus, allowing a much richer set of optimizations than traditional Register Transfer Level (RTL) based approaches. Moreover, raising the level of design abstraction allows to quickly evaluate the effect of different optimization on the overall area, performance and power. In addition, it allows to quickly generate system with particular area and performance trade-offs by simply setting different synthesis options' combinations. Experimental results setting different constraints show the effectiveness of our proposed approach.

High-Level Synthesis (HLS) is now part of most standard VLSI design flows and there are numerous commercial HLS tools available. One persistent problem of HLS is that the quality of results (QoR) still heavily depends on minor things like how the code is written. One additional observation that we have made in this work is that the input language used for the same HLS tool affects the QoR. HLS tools (commercial and academic) are built in a modular way which typically include a separate front-end (parser) for each input language supported. These front-ends parse the untimed behavioral descriptions, perform numerous technology independent optimizations and output a common intermediate representations (IR) for all different input languages supported. These optimizations also heavily depend on the synthesis directives set by the designer. These directives in the form of pragmas allow to control how to synthesize arrays (register or RAM), loops (unroll or not or pipeline) and functions (inline or not). We have observed that two functional equivalent behavioral descriptions with the same set of synthesis directives often lead to circuits with different QoR for the same HLS tool. Thus, automated approaches are needed to help designers to generate the best possible circuit independently of the input language used. To address this, in this work we propose using Graph Convolutional Networks (GCN) to determine the best language for a given new behavioral description and present an automated language converter for HLS.

Place and route tools do only consider area and timing when placing a synthesized netlist. This can lead to a placement with high-density power regions, which in turn lead to hotspots. This work presents a method to re-place logic cells locally, within the hotspot, to reduce the peak temperatures, leveraging the fact that placed rows contain fillers between cells. One key contribution of this work is that it optimizes all of the rows simultaneously instead of traditional methods that do a row-based optimization. This is accomplished by formulating the cell placement problem as a system of difference constraints (SDC). SDC constraint were mainly proposed to solve the operation scheduling in High-Level Synthesis. In this work we propose two methods that apply this global optimization problem for the thermal-aware re-placement of logic gates. Experimental results show that our proposed methods lead to better results than optimizing every row independently leading to average peak temperature reduction of 5.2°C and 9.5°C with minimum delay overhead.

Raising the level of VLSI design abstraction to the behavioral level allows to generate different micro-architectures from the same behavioral description by simply setting different synthesis options. These are typically synthesis directives in the form of pragmas that control how to synthesize arrays, loops, and functions. Out of all the combinations the designer is typically only interested in the synthesis directive combinations that lead to the Pareto-optimal designs. Unfortunately this multi-objective optimization problem grows supra-linearly with the number of the explorable operations. Thus, fast heuristics are needed. One additional way to accelerate the exploration process is by parallelizing the explorer tcreating multi-threaded versions. The main problem with this approach is that every time that a new pragma combination is generated the explorer requires to invoke the HLS process in order to evaluate the effect of these synthesis options on the resultant design. This tool invocation requires to check out a HLS tool license that will not be released until the HLS process has finished. This implies that the maximum number of parallel threads is limited by the number of licenses available. In the ASIC case, these licenses are extremely expensive, making it often prohibitory for some companies to have more than one. On contrary FPGA vendors provide their HLS tools free. Thus, it is tempting to investigate if FPGA HLS tools can be used to find the ASIC Pareto-optimal designs. To address this, in this work we present a dedicated multi-threaded parallel HLS DSE explorer that is able to accelerate HLS DSE for ASICs by targeting first FPGAs and using machine learning to convert the exploration results obtained to find the optimal ASIC equivalent. Experimental results show that our proposed approach is very efficient speedup up the exploration process considerably.

This works presents a design methodology to reoptimize legacy Register-Transfer level (RTL) designs specified in synthesizable Verilog or VHDL through High-Level Synthesis (HLS). The proposed methodology is based on an RTL to C compiler that converts synthesizable RTL descriptions into functional equivalent behavioral descriptions optimized to maximize its re-usability though HLS. This implies stripping off all the timing information from the RTL description and generating only C/C++ code that is functionally equivalent that has arrays, loops and functions. Generating these structures is very important in order to maximize the re-optimization potential as commercial HLS tools make extensive use of synthesis directives in the form or pragmas (comments) that allow HLS users to control how to synthesize them. E.g., loops can be fully unrolled, partially unrolled or pipelined, arrays can be synthesized as registers, memories or fully expanded into individual flip-flops and functions inline or not. Thus, generating C/C++ code with a larger number of these structures ensures that a larger variety unique implementations with different area vs. performance and power trade-offs can be generated from the converted C/C++ code. Experimental results with a variety of applications from different domains show the effectiveness of your proposed flow.

With most VLSI design companies now being fabless it is imperative to develop methods to protect their Intellectual Property (IP). One approach that has become very popular due to its relative simplicity and practicality is logic locking. One of the problems with traditional locking mechanisms is that the locking circuitry is built into the netlist that the VLSI design company delivers to the foundry which has now access to the entire design including the locking mechanism. This implies that they could potentially tamper with this circuitry or reverse engineer it to obtain the locking key. One relatively new approach that has been coined logic locking through omission, or hardware redaction, maps a portion of the design to an embedded FPGA (eFPGA). The bitstream of the eFPGA now acts as the locking key. This new approach has been shown to be more secure as the foundry has no access to the bitstream during the manufacturing stage. The obvious drawbacks are the increase in design complexity and the area and performance overheads associated with the eFPGA. In this work we propose, to the best of our knowledge, the first attack on these type of new locking mechanisms by substituting the exact logic mapped onto the eFPGA by a synthesizable predictive model that replicates the behavior of the exact logic. We show that this approach is applicable in the context of approximate computing where hardware accelerators tolerate certain degree of errors at their outputs. Experimental results show that our proposed approach is very effective finding suitable predictive models while simultaneously reducing the overall power consumption.

Raising the level of VLSI design abstraction from the Register Transfer Level (RTL) to the behavioral level has multiple advantages: (i) It reduces the turn-around-time, (ii) allows faster verification and (iii) extends the re-usability of the design as High-Level Synthesis (HLS) automatically re-optimizes the synthesized circuit when new process technologies are available by simply selecting a different technology library. Moreover, HLS makes extensive use of synthesis directives that control how to synthesize mainly loops (unroll or pipeline), arrays (register or RAM) and functions (inline or not). This further increases the re-usability of the behavioral code as it enables the generation of micro-architectures with different area vs. performance trade-offs. These advantages open the door to third party IP (3PIP) vendors providing Behavioral IPs (BIPs). Unfortunately, the market of third party BIPs is still very small and mostly limited to the HLS vendors themselves. Being so flexible is also their main weakness as it makes them only economically viable if the BIP provider can charge a large premium as it is highly unlikely that the BIP consumer will require their service again. Traditional IP vendors discriminate the price of the IP based on the amount of flexibility of the IP, e.g., RTL description vs. providing a synthesized gate netlist. We envision a similar price discrimination strategy for BIPs by limiting the re-usability of the BIP by partially encrypting the BIP source code. The main idea is to limit the search space, and hence, the re-usability of the BIP such that it only allows the BIP consumer to generate micro-architectures within a pre-defined search space range. This is accomplished by selectively fixing some of the synthesis directives in the form of pragmas at the source code while leaving others explorable. By encrypting the portion of the BIP that contains the fix pragmas we can guarantee that no designs outside of the pre-defined search space are generated. We believe that this work could serve as catalyst to grow the BIP market.

Approximate Computing has emerged as an alternative way to further reduce the power consumption of integrated circuits (ICs) by trading off errors at the output with simpler, more efficient logic. So far the main approaches in approximate computing have been to simplify the hardware circuit by pruning the circuit until the maximum error threshold is met. One of the critical issues, though, is the training data used to prune the circuit. The output error can significantly exceed the maximum error if the final workload does not match the training data. Thus, most previous work typically assumes that training data matches with the workload data distribution. In this work, we present a method that dynamically overscales the supply voltage based on different workload distribution at runtime. This allows to adaptively select the supply voltage that leads to the largest power savings while ensuring that the error will never exceed the maximum error threshold. This approach also allows restoring of the original error-free circuit if no matching workload distribution is found. The proposed method also leverages the ability of High-Level Synthesis (HLS) to automatically generate circuits with different properties by setting different synthesis constraints to maximize the available timing slack and, hence, maximize the power savings. Experimental results show that our proposed method works very well, saving on average 47.08% of power as compared to the exact output circuit and 20.25% more than a traditional approximation method.

The quest to democratize the use of Field-Programmable Gate Arrays (FPGAs) has given High-Level Synthesis (HLS) the final push to be widely accepted with FPGA vendors strongly supporting this VLSI design methodology to expand the FPGA user base. HLS takes as input an untimed behavioral description and generates efficient RTL (Verilog or VHDL). One major advantage of HLS is that it allows us to generate a variety of different micro-architectures from the same behavioral description by simply specifying different combination of synthesis options. In particular, commercial HLS tools make extensive use of synthesize directives in the form pragmas. This strength is also a weakness as it forces HLS users to fully understand how these synthesis options work and how they interact to efficiently set them to get a hardware implementation with the desired characteristics. Luckily, this process can be automated. Unfortunately, the search space grows supra-linearly with the number of synthesis options. To address this, this work proposes an automatic synthesis option tuner dedicated for FPGAs. We have explored a larger number of behavioral descriptions targeting ASICs and FPGAs and found out that due to the internal structure of the FPGA a large number of synthesis options combinations never lead to a Pareto-optimal design and, hence, the search space can be drastically reduced. Moreover, we make use of large database of DSE results that we have generated since we started working in this field to further accelerate the exploration process. For this, we use a technique based on perceptual hashing that allows our proposed explorer to recognize similar program structures in the new description to be explored and match them with structures in our database. This allows us to directly retrieve the pragma settings that lead to Pareto-optimal configurations. Experimental results show that the search space can be accelerated substantially while leading to finding most of the Pareto-optimal designs.

The protection of Intellectual Property (IP) has emerged as one of the most important issues in the hardware design industry. Most VLSI design companies are now fabless and need to protect their IP from being illegally distributed. One of the main approach to address this has been through logic locking. Logic locking prevents IPs from being reversed engineered as well as overbuilding the hardware circuit by untrusted foundries. One of the main problem with existing logic locking techniques is that the foundry has full access to the entire design including the logic locking mechanism. Because of the importance of this topic, continuous more robust locking mechanisms are proposed and equally fast new methods to break them appear. One alternative approach is to lock a circuit through omission. The main idea is to selectively map a portion of the IP onto an embedded FPGA (eFPGA). Because the foundry does not have access to the bitstream, the circuit cannot be used until programmed by the legitimate user. One of the main problems with this approach is the large overhead in terms of area and power, as well as timing degradation. Area is especially a concern for price sensitive applications. To address this, in this work we presents a method to map portions of a design onto a Coarse Grained Runtime Reconfigurable Architecture (CGRRA) such that multiple parts of a design can be hidden onto the CGRRA, substantially amortizing the area overhead introduced by the CGRRA.

High-Level Synthesis (HLS) dramatically facilitates the design and verification of individual components. These components are typically the dedicated hardware accelerators used within larger systems, e.g. image processing, DSP or encrypheterogeneoustion cores. Unfortunately, HLS is a single process (component) synthesis method. This implies that the integration of these accelerators are often done at the RT-Level, which implies that the system-level verification and co-design needs to be done at lower levels of abstraction. This work presents an approach that enables a path to generate complete SoCs at the behavioral level. Two main contributions that enable this are: First, an automatic bus generator that generates a synthesizable behavioral description of standard on-chip buses. Second, a library of synthesizable APIs that allow any component in the system to send or receive data through the bus. This approach has significant advantages over traditional approaches. (1) It enables the generation of fast cycle-accurate simulation models of the entire SoC. Experimental results for SoCs of different complexities show that an average speedup of $7.6\times$ is achieved. (2) It allows to completely separate the bus implementation details from the developers view allowing the change between bus types and configuration with only minor changes in the designers’ code. Finally, (3) by creating synthesizable SystemC code any commercial HLS tool can convert the given bus and bus interface code into efficient RTL, thus, making our proposed flow HLS tool agnostic.

This paper proposes a practical method to watermark behavioral IP (BIPs) for High-Level Synthesis (HLS), such that the watermark can be unequivocally retrieved at the generated RTL code, while being unremovable. The main approaches to watermark BIPs so far have focus on modifying the HLS process by e.g. introducing watermarking-aware scheduling or register binding algorithms. The main problem with these approaches is that they involve having full control over the HLS tool's internal behavior, which is not practically possible. Specifically, state-of-the-art HLS tools do not allow this type of controllability. Hence, these approaches are currently impossible to be implemented. On the other hand, commercial HLS tools make extensive use of synthesis directives in the form of pragmas. In this work we make use of these synthesis directives to assign operations in the source code to specific functional units given in the technology library in order to create the watermark. Experimental results show that our proposed method is effective in creating strong watermarks, while practical at the same time.

Behavioral IPs (BIPs) have one salient advantage compare to the traditional RTL IPs given in Verilog or VHDL. The BIP can be used to generate RTLs with very different characteristics by simply specifying different synthesis directives. These synthesis directives are typically specified at the source code in the form of pragmas (comments) and control how to synthesize arrays (e.g. registers or RAM), loops (unroll or fold) and functions (inline or not). This allows a BIP consumer to purchase a BIP once and re-use it in future projects by simply specifying a different mix of these synthesis directives. This would obviously not benefit the BIP provider as the BIP consumer would not need to purchase the BIP again for future projects as oppose to IPs bought at the RT or gate-netlist level. To address this, this work presents a method to enable the BIP provider to lock the search space of the BIP such that the user can only generate micro-architectures within a specified search space. This leads to significant benefits to both parties: The BIP provider can now discriminate the BIP price based on how much of the search space is made visible to the BIP consumer, while the BIP consumer benefits from a cheaper BIP, albeit limited in its search space. This approach is made possible through partial encryptions of the BIP. Thus, this work presents a method that selectively fixes some synthesis directives and allows the BIP user to modify the rest of the directives such that the micro-architectures generated are guaranteed to be within the pre-defined search space.

Approximate computing has emerged as a powerful alternative to further reduce the power of integrated circuits (ICs). The main idea is to simplify the software or hardware circuit to trade off lower power with a certain output error. This work presents a method to unlock approximations that under traditional approaches would have been ignored. In particular, we focus on Variable to Variable (V2V) and Variable to Constant (V2C) approximations in behavioral descriptions for either embedded software or High-Level Synthesis (HLS). The main idea in V2V and V2C is to substitute the computation of a variable by either another variable computed previously in the code or a constant to trade-off code size or circuit size with output error. Although these approximations are very powerful, we observed that they rarely occur. To enable these powerful approximations, we propose an automatic source code refactoring method combined with the selective substitution of portions of the code with predictive models. To maximize the savings in terms of code size, area, or power, we also propose an automated search method that finds the smallest possible predictive model for a given error threshold. Experimental results targeting a TI MSP430 processor as well as HLS show that our proposed method is very effective.

Approximate computing has shown to be an effective approach to generate smaller and more power-efficient circuits by trading the accuracy of the circuit vs. area and/or power. So far, most work on approximate computing has focused on specific components within a system. It severely limits the approximation potential as most Integrated Circuits (ICs) are now complex heterogeneous systems. One additional limitation of current work in this domain is they assume that the training data matches the actual workload. This is nevertheless not always true as these complex Systems-on-Chip (SoCs) are used for a variety of different applications. To address these issues, this work investigates if lower-power designs can be found through mixing approximations across the different components in the SoC as opposed to only aggressively approximating a single component. The main hypothesis is that some approximations amplify across the system, while others tend to cancel each other out, thus, allowing to maximize the power savings while meeting the given maximum error threshold. To investigate this, we propose a method called ADAPT. ADAPT uses a neural network-based controller to dynamically adjust the supply voltage (Vdd) of different components in SoC at runtime based on the actual workload.

VLSI design companies are now mainly fabless and spend large amount of resources to develop their Intellectual Property (IP). It is therefore paramount to protect their IPs from being stolen and illegally reversed engineered. The main approach so far to protect the IP has been to add additional locking logic such that the circuit does not meet the given specifications if the user does not apply the correct key. The main problem with this approach is that the fabless company has to submit the entire design, including the locking circuitry, to the fab. Moreover, these companies often subcontract the VLSI design back-end to a third-party. This implies that the third-party company or fab could potentially tamper with the locking mechanism. One alternative approach is to lock through omission. The main idea is to judiciously select a portion of the design and map it onto an embedded FPGA (eFPGA). In this case, the bitstream acts as the logic key. Third party company nor the fab will, in this case, have access to the locking mechanism as the eFPGA is left un-programmed. This is obviously a more secure way to lock the circuit. The main problem with this approach is the area, power, and delay overhead associated with it. To address this, in this work, we present a framework that takes as input an untimed behavioral description for High-Level Synthesis (HLS) and automatically extracts a portion of the circuit to the eFPGA such that the area overhead is minimized while the original timing constraint is not violated. The main advantage of starting at the behavioral level is that partitioning the design at this stage allows the HLS process to fully re-optimize the circuit, thus, reducing the overhead introduced by this obfuscation mechanism. We also developed a framework to test our proposed approach and plan to release it to the community to encourage the community to find new techniques to break the proposed obfuscation method.

High-Level Synthesis (HLS) allows to synthesize untimed behavioral descriptions into efficient RTL descriptions (Verilog or VHDL). One key advantage of HLS is that it allows to generate different micro-architectures from the same behavioral description by simply specifying different mixes of synthesis options. These include, how to synthesize arrays (e.g. RAM or registers), loops (unroll completely, partially or not unroll or pipeline) and functions (inline or not). Ideally, the designer would like to find a mix that leads to the smallest and fastest microarchitecture. However, these design parameters are conflicting which means that there is not a single optimal solution but a range of solutions that form a Pareto-front. Out of all the possible synthesis combinations, the most important ones are the ones that lead to Pareto-optimal micro-architectures that form this front. Thus, automatic HLS design space exploration methods are desirable to efficiently find these micro-architectures automatically. This work investigates how formulating the cost function affects the quality of the exploration and its runtime and proposes a new cost function that leads to better results compared to the traditional formulation based on weighted-sum of the design metrics. We show that the newly proposed cost function leads to better results for three well-known meta-heuristics. In particular simulated annealing, genetic algorithm and ant-colony optimization.

Many applications tolerate errors at their outputs. Some examples include image and digital signal processing applications. At the same time these applications are often used in systems that require high degrees of fault-tolerance. Examples include autonomous driving applications. Thus, in this work we propose a method to reduce the complexity of hardware redundant systems that are amenable to approximate computing such that soft errors outside a maximum specified threshold are detected. This leads to the detection of catastrophic errors, while allowing the system to continue functioning when smaller single event upsets (SEU) occur. The proposed method reduces the complexity of the duplicated module by applying a set of approximations in such a way that the output is guaranteed to operate within a given error range with the exact module. Experimental results show that the proposed approach works well and that area saving between 30% and 19% can be achieved on average for different error ranges compared to the traditional exact duplication with compare approaches.

Approximate computing has shown to be an effective approach to generate smaller and more power-efficient circuits by trading the accuracy of the circuit vs. area/power. So far, most work on approximate computing has focused on specific components within a system. This severely limits the approximation potential as most Integrated Circuits (ICs) are now complex heterogeneous systems. This paper investigates if lower-power designs can be found through mixing approximations across the different components in the SoC as opposed to only aggressively approximating a single component. The main hypothesis is that some approximations amplify across the system, while others tend to cancel each other out, thus, allowing to maximize the power savings while meeting the given maximum error threshold. In this work, we consider the Analog-to-Digital Converter (ADC), CPU, hardware accelerators, and interconnect between all these components. Moreover, to quickly measure the effect of different approximation mixes, we have developed a framework that allows generating complete SoCs at the behavioral level through a bus generator and a library of synthesizable bus interfaces. This enables the use of fast simulation models (transaction and cycle-accurate) to accurately measure the error at the system’s output while measuring the benefit in terms of area or energy reduction of different mixes of approximations. Experimental results show that taking into account the entire system as oppose to only individual components leads to an additional average energy savings of 14% to 17% for different maximum error thresholds and the best case up to 39%.

Among various competing designs targeting similar functionality, the key differentiator typically consists of a small amount of custom Intellectual Property (IP). To protect this IP from reverse engineering, designers need effective solutions for hiding the unique aspects of their implementations. In this work, we introduce a general framework for partitioning the computation performed by a design into a part whose implementation is commonly known (and encountered across many designs), and a part which is unique to this design. The former can then be built using conventional techniques (including untrusted manufacturing facilities) while the latter needs to be protected using additional obfuscation techniques. The existence of several other known implementations of the (same or similar) target function serves as a decoy which deflects efforts seeking to reverse-engineer the unique implementation. We demonstrate our framework using a hardware accelerator case study where (a) partitioning is performed through High Level Synthesis (HLS), (b) the commonly known portion of the accelerator is implemented as an Application Specific Integrated Circuit (ASIC), and (c) the unique portion of the accelerator is implemented on an embedded Field-Programmable Gate Array (eFPGA).

Raising the level of VLSI design abstraction to C leads to many advantages compared to the use of low-level Hardware Description Languages (HDLs). One key advantage is that it allows the generation of micro-architectures with different trade-offs by simply setting unique combinations of synthesis options. Because the number of these synthesis options is typically very large, exhaustive enumerations are not possible. Hence, heuristics are required. Meta-heuristics like Simulated Annealing (SA), Genetic Algorithm (GA) and Ant Colony Optimizations (ACO) have shown to lead to good results for these types of multi-objective optimization problems. The main problem with these meta-heuristics is that they are very sensitive to their hyper-parameter settings, e.g. in the GA case, the mutation and crossover rate and the number of parents pairs. To address this, in this work we present a machine learning based approach to automatically set the search parameters for these three meta-heuristics such that a new unseen behavioral description given in C can be effectively explored. Moreover, we present an exploration technique that combines the SA, GA and ACO together and show that our proposed exploration method outperforms a single meta-heuristic.

Shrinking transistor sizes are jeopardizing the reliability of runtime reconfigurable Field Programmable Gate Arrays (FPGAs), making them increasingly sensitive to aging effects such as Negative Bias Temperature Instability (NBTI). This paper introduces a reliability-aware floorplanner which is tailored to multi-context, coarse-grained, runtime reconfigurable architectures (CGRRAs) and seeks to extend their Mean Time to Failure (MTTF) by balancing the usage of processing elements (PEs). The proposed method is based on a Mixed Integer Linear Programming (MILP) formulation, the solution to which produces appropriately-balanced mappings of workload to PEs on the reconfigurable fabric, thereby mitigating aging-induced lifetime degradation. Results demonstrate that, as compared to the default reliability-unaware floorplanning solutions, the proposed method achieves an average MTTF increase of 2.5× without introducing any performance degradation.

This work proposes a method to accelerate the process of High-Level Synthesis (HLS) Design Space Exploration (DSE) by pre-characterizing micro-kernels offline and creating predictive models of these. HLS allows to generate different types of micro-architectures from the same untimed behavioral description. This is typically done by setting different combinations of synthesis options in the form or synthesis directives specified as pragmas in the code. This allows, e.g. to control how loops should be synthesized, arrays and functions. Unique combinations of these pragmas leads to micro-architectures with a unique area vs. performance/power trade-offs. The main problem is that the search space grows exponentially with the number of explorable operations. Thus, the main goal of efficient HLS DSE is to find the synthesis directives' combinations that lead to the Pareto-optimal designs quickly. Our proposed method is based on the pre-characterization of micro-kernels offline, creating predictive models for each of the kernels, and using the results to explore a new unseen behavioral description using compositional methods. In addition, we make use of perceptual hashing to match new unseen micro-kernels with the pre-characterized micro-kernels in order to further speed up the search process. Experimental results show that our proposed method is orders of magnitude faster than traditional methods.

High-level synthesis (HLS) takes as input a behavioral description (e.g. C/C++) and generates efficient hardware through three main steps: allocation, scheduling, and binding. The scheduling step, times the operations in the behavioral description by scheduling different portions of the code at unique clock steps (control steps). The code portions assigned to each clock step mainly depend on the target synthesis frequency and target technology. This work makes use of this to generate smaller and faster circuits by approximating the program portions scheduled in each clock step and by exploiting the slack between different scheduling step to further increase the performance/reduce the latency of the resultant circuit. In particular, each individual scheduling step is approximated given a maximum error boundary and a library of different approximation techniques. In order to further optimize the resultant circuit, different scheduling steps are merged based on the timing slack of different control step without violating the given timing constraint (target frequency). Experimental results from different domain-specific applications show that our method works well and is able to increase the throughput on average by 82% while at the same time reducing the area by 21% for a given maximum allowable error.

Many emerging applications require simple controllers that run the exact same application continuously. These include medical devices and IoTs of different nature. Because of the nature of these applications, they have to be ultra-low power and small. Most of the applications mapped onto low-power processors are computationally inexpensive, thus, amenable to be executed on a simple microprocessor. One of the problems of using a general purpose processor, is that not all of the resources are needed for a specific application, thus, there is a large potential for simplifying the processor to achieve lower area and power (static and dynamic). In addition, these processors can be specified at the behavioral level and use High-Level Synthesis (HLS) to generate the RTL automatically. This opens a window to additional optimizations as the processor can be pruned and re-synthesized at different VLSI design levels in order to obtain a smaller and more power-efficient processor. This work presents a methodology to customize a behavioral RISC processor automatically for a given workload such that its area and power are significantly reduced as compared to the original processor. Compared to previous work that customizes a given processor at the gate netlist only, our proposed method also shows significant benefits. In particular, we show that raising the level of abstraction reduces the area and power by 78.3 % and 70.1%.

Raising the level of VLSI design abstraction from RT-level to the behavioral level poses new challenges, but also new opportunities to make the hardware robust against single-event upsets (SEUs). In this paper, we propose a new method based on the light-weight detection mechanism of data distribution of the internal signals to detect soft-errors. In particular, we study the case of how resource sharing affects the ability to detect SEUs and present comprehensive results highlighting the benefits of resources sharing to make hardware circuits more fault-tolerant. Resources sharing is typically a tedious work at the RT-level because a state machine has to be inserted to control sharing mechanism (typically muxes) of the functional unit inputs. Resources sharing can nevertheless fully automated in High-Level Synthesis (HLS). Thus, our proposed method shows that automated HLS resource sharing enables low-cost fault-tolerant designs.

In this article, we introduce an automatic stream computing reoptimization flow from ASICs to field-programmable gate arrays (FPGAs). Complex VLSI designs need to be prototyped and/or emulated on FPGAs. The main problem that we address in this article is that configurations optimized when targeting ASICs are often, as we will show in this article, highly un-optimal when remapped onto an FPGA. Thus, this article proposes a method to first generate a variety of dataflow configurations targeting an ASIC given multiple behavioral descriptions for high-level synthesis (HLS) and then, based on a compositional predictive model, automatically reoptimize the dataflow when mapped onto an FPGA. The experimental results show that our proposed method works well and that it is very fast.

This article presents a survey of the different modern high-level synthesis (HLS) design space exploration (DSE) techniques that have been proposed so far to automatically generate hardware accelerators of different tradeoffs. HLS has multiple advantages compared to traditional RT-level-based hardware design. One key advantage is that a variety of different microarchitectures of unique tradeoffs can be obtained from the same untimed behavioral description by setting different synthesis options. Out of all the possible microarchitectures, the one that the designers are most interested in are the Pareto-optimal ones. The main problem is that the search space grows superlinearly with the number of synthesis options, and hence, heuristics have been proposed to search the space efficiently. This article summarizes the main techniques proposed and addresses the critical issues still not resolved as well identifies new opportunities in this field. It also serves as a guide for anyone wanting to create their own HLS DSE.

One of the advantages of High-Level Synthesis (HLS), also called C-based VLSI-design, over traditional RT-level VLSI design flows, is that multiple micro-architectures of unique area vs. performance can be automatically generated by setting different synthesis options, typically in the form of synthesis directives specified as pragmas in the source code. This design space exploration (DSE) is very time-consuming and can easily take multiple days for complex designs. At the same time, and because of the complexity in designing large ASICs, verification teams now routinely make use of emulation and prototyping to test the circuit before the silicon is taped out. This also allows the embedded software designers to start their work earlier in the design process and thus, further reducing the Turn-Around-Times (TAT). In this work, we present a method to automatically re-optimize ASIC designs specified as behavioral descriptions for HLS to FPGAs for emulation and prototyping, based on the observation that synthesis directives that lead to efficient micro-architectures for ASICs, do not directly translate into optimal micro-architectures in FPGAs. This implies that the HLS DSE process would have to be completely repeated for the target FPGA. To avoid this, this work presents a predictive model-based method that takes as inputs the results of an ASIC HLS DSE and automatically, without the need to re-explore the behavioral description, finds the Pareto-optimal micro-architectures for the target FPGA. Experimental results comparing our predictive-model based method vs. completely re-exploring the search space show that our proposed method works well.

Widespread adoption of the fabless business model and utilization of third-party foundries have increased the exposure of sensitive designs to security threats such as intellectual property (IP) theft and integrated circuit (IC) counterfeiting. As a result, concerted interest in various design obfuscation schemes for deterring reverse engineering and/or unauthorized reproduction and usage of ICs has surfaced. To this end, in this paper we present a novel mechanism for structurally obfuscating sensitive parts of a design through post-fabrication TRAnsistor-level Programming (TRAP). We introduce a transistor-level programmable fabric and we discuss its unique advantages towards design obfuscation, as well as a customized CAD framework for seamlessly integrating this fabric in an ASIC design flow. We theoretically analyze the complexity of attacking TRAP-obfuscated designs through both brute-force and intelligent SAT-based attacks and we present a silicon implementation of a platform for experimenting with TRAP. Effectiveness of the proposed method is evaluated through selective obfuscation of various modules of a modern microprocessor design. Results corroborate that, as compared to an FPGA implementation, TRAP-based obfuscation offers superior resistance against both brute-force and oracle-guided SAT attacks, while incurring an order of magnitude less area, power and delay overhead.

Fault tolerance is vital in many domains. One popular way to increase fault-tolerance is through hardware redundancy. However, basic redundancy cannot cope with Common Mode Failures (CMFs). One way to address CMF is through the use of diversity in combination with traditional hardware redundancy. This work proposes an automatic design space exploration (DSE) method to generate optimized redundant hardware accelerators with maximum diversity to protect against CMFs given as a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over the traditional RT-level design based on low-level Hardware Description Languages (HDLs): The ability to generate micro-architectures with unique characteristics from the same behavioral description. Experimental results show that the proposed method provides a significant diversity increment compared to using traditional RTL-based exploration to generate diverse designs.

Commercial High-Level Synthesis (HLS) tool vendors have started to enable ways to protect Behavioral IP (BIPs) from being unlawful used. The main approach is to provide tools to encrypt these BIPs which can be decrypted by the HLS tool only. The main problem with this approach is that encrypting the IP does not allow BIP users to insert synthesis directives into the source code in the form of pragmas (comments), and hence cancels out one of the most important advantages of C-based VLSI design: The ability to automatically generate micro-architectures with unique design metrics, e.g. area, power and performance. This work studies the impact to the search space when synthesis directives are not able to be inserted in to the encrypted IP source code while other options are still available to the BIP users (e.g. setting global synthesis options and limiting the number and type of functional units) and proposes a method that selectively controls the search space by encrypting different portions of the BIP. To achieve this goal we propose a fast heuristic based on divide and conquer method. Experimental results show that our proposed method works well compared to an exhaustive search that leads to the optimal solution.

This paper presents an FPGA-based hardware acceleration of the design diversity calculation to build robust redundant hardware systems against common model failures. We exploit the benefits of C-based VLSI design to generate a design pool of micro-architectures with unique characteristics from the same behavioral description. To identify the most diverse design pairs from this massive design pool, a computationally-intensive fault-injection based process is needed. Thus, in this work, we leverage the use of FPGAs to accelerate the design diversity calculation. Experimental results show an average of 2x speedup compared to a traditional software implementation. We also show that much higher speedups can be achieved when using larger FPGAs that can host a larger pool of designs.

This work investigates if temperature can be used to fingerprint FPGA designs and presents a method to generate a large number of functionally equivalent FPGA designs such that each design has a unique distinguishable thermal signature. The main methodology behind this work is based on the design space exploration of each hardware accelerator in the design specified as a behavioral description (e.g. ANSI-C, C++ or SystemC) to obtain a trade-off curve of designs with unique area vs. performance trade-offs as well as a third dimension that consists of the difference in their thermal profle. Experimental results, prototyping different hardware accelerators on a FPGA, and using a high resolution infrared camera, show the usability of our proposed method, which is able to distinguish between the different design versions and hence can serve to detect if an FPGA design is unlawfully being used.

The protection of Intellectual Property (IP) has emerged as one of the most serious areas of concern in the semiconductor industry. To address this issue, we present a method and architecture to map selective portions of a design, given as a behavioral description for High-Level Synthesis (HLS) to a high-security embedded Field-Programmable Gate Array (eFPGA). In this manner, only the end-user has access to the full functionality of the chip. Using six benchmark circuits, we show that our approach is effective. In all cases, the Time-To-Break (TTB) is so long (at least 8 million hours) that for all practical purposes the designs are secure while incurring area overheads of around 5%. Further, latencies were only slightly increased, while the computation times are under one minute.

High-Level Synthesis (HLS) allows the automatic generation of hardware accelerators with unique design metrics. This work leverages this unique feature and presents a method to increase the search space of fault-tolerant hardware accelerators. The proposed method is based on a two-stage approach that automatically generates Pareto-optimal configurations for the hardware accelerators with different area, performance and reliability to mitigate the effect of soft errors. The first stage performs a source-to-source transformation on the behavioral description to annotate the N-modular redundancy directly at the source code including the voter, while the second stage then performs a HLS design space exploration (DSE) on this newly obtained behavioral description. Compared to performing the exploration on a single module and then replicating the accelerator N times, the proposed exploration strategy leads to a much richer search space. Experiments show that our proposed method leads to better results compared to the state-of-the-art by expanding the search space considerably.

This work presents a method to selectively extract portions of a behavioral description to be synthesized as a hardware accelerator using High-Level Synthesis (HLS) onto different predictive models in order to trade-off the accuracy of the accelerators' outputs with area and power. Because the main aim of this work is to synthesize the newly approximated behavioral description, we investigate the use of different predictive models, mainly linear regression (LR) and multi-layer perceptron (MLP), highlighting the trade-offs of using one over the other. In addition, we further extend the search space by reducing the precision of the predictive models' coefficients, thus, leading to a wider range of solutions. Experimental results using a variety of benchmarks from different domains show that our proposed method works well compared to another state of the art approximate solution.

This paper presents a method to generate a variety of micro-architectures for a given hardware accelerator mapped onto reconfigurable fabric optimized for different operating frequencies. The most optimal micro-architecture is then loaded onto the fabric for a given operating frequency in order to minimize the power consumption. State-of-the-art FPGAs are runtime reconfigurable and provide multiple clock domains. This enables these devices to reconfigure any accelerator mapped on them and their frequencies at runtime. At the same time, FPGA vendors have embraced High-Level Synthesis (HLS) to increase the design productivity and help designers with limited hardware development skills to program these devices. One of the advantages of HLS over traditional RT-level hardware design is that HLS allows to automatically generate micro-architectures with unique area, performance and power trade-offs by setting different synthesis options, which is impractical or very time consuming at the RT-level. This work leverages these two features and investigates the benefit of adapting the micro-architecture of hardware accelerators mapped onto a reconfigurable fabric at runtime when the operating frequency changes to reduce the power consumption, while maximizing the throughput. To enable the frequency-aware micro-architectural adaptation we also propose a simple micro-architectural resource manager and show that the overhead in terms of area and delay is negligible. We conduct two sets of experiments. The first shows that our proposed approach leads to faster circuits which consume less power than just statically scaling the frequency of the fastest micro-architecture for a variety of different test cases. The second case, presents case study of a face detection application mapped onto a battery-operated wireless camera sensor node powered by solar cells.

In this work, we propose a method that automatically generates a set of functional equivalent systems with unique performance vs. peak temperature, where the starting point is a set of behavioral descriptions for High-Level Synthesis (HLS), and the output the Pareto-optimal systems. This is accomplished by leveraging one of the main benefits of C-based VLSI design: The ability to automatically create functional equivalent circuits with unique area vs. performance trade-offs from a single behavioral description. The proposed method is built around three main phases. The first phase performs a design space exploration on each module given as a behavioral description for HLS to obtain a trade-off curve of dominating micro-architectures. The second phase builds different systems by combining different mixes of micro-architectures. Finally, phase 3 continues by selectively floorplanning these micro-architectures in the system to obtain a trade-off curve of Pareto-optimal systems. Experimental results targeting a FPGA show that our proposed method works well.

Hardware redundancy techniques are extensively used for enhancing system reliability, availability and fault tolerance. However, traditional identical module N-modular redundancy (NMR) cannot protect against Common Mode Failures (CMFs). One method that has been proposed to protect against CMFs is the use of dissimilar (diverse) module redundancy. One of the problems with previous work is that it generates these diverse modules by perturbing the gate-netlist and thus, achieve very limited diversity. In addition, previous work is very time consuming as it requires to insert fault-pairs in the gate-netlists in order to measure the effect of these on the outputs. To address these issues, this work proposes to first increase diversity by raising the level of abstraction from the gate level to the behavioral level. Secondly, we propose a fast machine learning based method that facilitates the design space exploration (DSE) of single behavioral descriptions in order to generate optimized redundant hardware accelerator system with maximum diversity to protect against CMFs. For this purpose, this work exploits one of the main advantages of C-based VLSI design: The ability to generate micro-architectures with unique characteristics from the same behavioral description by setting different synthesis directives in the form of pragmas. Experimental results show that our proposed method is a fast and efficient way to generate diverse designs to protect the system against CMFs.

This paper presents a method to improve the performance and reduce the energy of applications mapped onto coarse-grain runtime reconfigurable arrays (CGRRAs) by substituting and merging different contexts by approximate predictive models. In CGRRAs applications are split into contexts. The CGRRA is then reconfigured every clock cycle by loading a new context onto the reconfigurable fabric. In this work, we propose to substitute contexts by approximate expressions using machine learning models of different complexities like linear regression (LR) and multi-layer perceptrons (MLPs) such that the CGRRA area and energy can be reduced albeit introducing different levels of errors at the output. Moreover, we propose a technique to merged these approximated contexts with other contexts leading to a set of Pareto-optimal configurations. Experimental results show that our proposed method works well and it can trade-off area, performance and energy with output error of several computationally intensive applications mapped onto a commercial CGRRA.

VLSI design teams have vast amounts of legacy RTL code that has been manually optimized to execute a particular task within a given performance, area, and power budget. The main problem is that these fixed architectures cannot be easily re-used in future projects which require different performance, area and power constraints mixes. Thus, in this work we introduce a method to abstract RTL descriptions into synthesizable behavioral descriptions which in turn allow the generation of a new micro-architecture with the newly desired characteristics. In particular, this work, presents a set of optimizations that allow to generate a larger number of micro-architectures compared to the state-of-the-art RTL to C compilers based on two main optimizations: Array merging and loop fusing. Experimental results show that our optimization method is efficient in extending the variety of micro-architectures found and hence increasing the re-usability of these designs.

Many applications show tolerance to inaccuracies. These can be exploited to build faster circuits with smaller area and lower power. This is particularly true for the hardware accelerators in heterogeneous computing systems. A major problem with approximate computing is that the resulting approximated circuit is highly dependent on the training data. Previous works often rely on static training results. If the workload is dynamic in nature or changes over time, output errors may reach unacceptable levels. Therefore, dynamic control methods are needed to solve this problem. To address this issue, in this paper, we propose an approximate self-adaptive architecture that autotunes itself at runtime based on the workload. Two different control mechanisms are proposed, one based on a regular heartbeat (HB), which resets the approximate circuits at regular intervals and the other based on internal lightweight checkers (LWCs). These checkers detect a change in the workload and reset the approximations. Experimental results show that our proposed methods work well leading to very good results compared to other approximation methods while keeping the output error within the given maximum error threshold at relatively low-area overheads, on average 8% and 8.5% for HB and LWC method, respectively, and delay overheads 5.9% and 8.1%.

Continuous pursuit of higher performance and energy efficiency has led to heterogeneous SoC that contains multiple dedicated hardware accelerators. These accelerators exploit the inherent parallelism of tasks and are often tolerant to inaccuracies in their outputs, e.g. image and digital signal processing applications. At the same time, permanent faults are escalating due to process scaling and power restrictions, leading to erroneous outputs. To address this issue, in this paper, we propose a low-cost, universal fault-recovery/repair method that utilizes supervised machine learning techniques to ameliorate the effect of permanent fault(s) in hardware accelerators that can tolerate inexact outputs. The proposed compensation model does not require any information about the accelerator and is highly scalable with low area overhead. Experimental results show, the proposed method improves the accuracy by 50% and decreases the overall mean error rate by 90% with an area overhead of 5% compared to execution without fault compensation.

This paper investigates the effect of pin multiplexing on the resultant micro-architecture of synthesizable behavioral descriptions for High-Level Synthesis (HLS). A method is presented to find the most efficient pin assignments by assigning multiple logic inputs and outputs to the same physical ports such that the performance degradation and area overhead is minimized. The proposed method is a fast heuristic based on the scheduling results of HLS seen as a black box and hence is flexible enough to work with any HLS tool. Experimental results show that our proposed method is very efficient compared to an exhaustive search and a simulated annealing method at a fraction of the time and much better than randomly selecting the pins to be multiplexed.

In this work we propose to isolate and encapsulate into exact-approximate tiles, that we call EXAP-tiles, individual approximations in hardware accelerators mapped onto FPGAs. These approximate hardware accelerators are enhanced with a controller that can dynamically enable or disable these EXAPtiles at runtime. This allows to trade-off dynamically, at runtime, the output error vs. e.g. the reduction in power. In particular, in this work we make use of this feature to dynamically control the temperature of the hardware accelerator by selectively enabling and disabling the EXAP-tiles. We have implemented two control methods: The first, based on the static pre-characterization of each EXAP-tile and the second, based on the closeness of the tile to the hotspot. We have prototyped the system on a Terasic DE1-SoC FPGA board and show the effectiveness of the proposed framework.

Approximate computing has become a promising methodology to create energy-efficient circuits by leveraging the inherent tolerance of application to errors. At the same time, runtime reconfigurable architectures are being proposed to deal with the increase in complexity of today's circuits and high Non-Recurring Engineering (NRE) costs (either stand-alone or embedded in SoCs). These runtime reconfigurable architectures are typical coarse grain (CGRRA) and are programmed by synthesizing a given application into a set of contexts which continuously configure the CGRRA at runtime. Applications mapped onto these architectures pose unique challenges when approximated. E.g. partitioning an application into a large number of contexts can limit the depth of the approximation to the context itself, while having a smaller number of contexts increases the overall CGRRA area (time multiplexing the application reduces the area by the multiplexing ratio), but maximizes the effect of the different approximation optimizations. Thus, this work studies the effect of different context granularities when mapping an application to be approximated onto a CGRRA, exposing the different trade-offs and proposes a method to create the context sizes of different granularities to minimize the energy under a maximum error constraint. The input of the proposed method is a behavioral description (ANSI-C or SystemC) for High-Level Synthesis (HLS). Results show that our proposed method is able to generate approximate circuits that are much more energy-efficient than other methods as well as leading to similar results compared to an exhaustive search method that leads to the optimal solution while being 25x faster.

This work proposes an automatic method to generate optimized redundant hardware accelerator with maximum reliability given a single behavioral description for High-Level Synthesis (HLS). For this purpose, this work exploits one of the main advantages of C-based VLSI design over traditional RT- level design: The ability to generate micro-architectures with unique characteristics from the same behavioral description. This is typically done by setting different synthesis options to determine how to synthesize loops, arrays and functions and to specify the number and type of Functional Units (FUs) to be instantiated. The proposed method is composed of two main phases. The first phase performs HLS Design Space Exploration (DSE) leading to a trade-off curve of designs with a unique area, execution time and reliability. The second phase finds the most reliable system given an area and time constraint by either implementing time or space redundancy, or a mixture of both using any combinations of micro-architectures found by the explorer. This second phase has been formulated as an integer linear program (ILP). Experimental results show that the proposed method provides a 20% reliability increase compared to the most common approach of simply using a single micro-architecture and instantiating it multiple times with no significant area or timing overhead.

With the continuous sub-micron process scaling, reliability of integrated circuits has quickly become a first-order design concern. In modern computing systems, transient errors are increasingly likely to corrupt the computation by altering the control flow or sequencing of instructions, leading to catastrophic failures. Prior work on control flow checking provides good coverage but at a high cost. In this paper, by exploring regular control flow patterns found in most applications, we propose the optimization schemes for software signature control flow checking that could reduce the error detection overheads. Specifically, we leverage the fact that most applications have: (1) simple fan-in / fan-out control flow patterns, and (2) most of control flows can be predicted during the compilation stage through static branch prediction heuristics. By exploiting these opportunities, we propose two techniques to reduce the number of inserted codes at common paths and simplify control flow checking of irregular patterns with minimal overheads. Experimental results on a variety of applications demonstrate that our approaches could reduce checking overhead by almost 2.5x on average while leading to similar fault coverage compared to traditional control flow checking.

C-based VLSI design some distinct advantages over traditional RT-Level VLSI design. One key advantage is the ability to automatically generate different types of microarchitectures from the original behavioral description. This allows to explore the design space obtaining micro-architectures with unique characteristics. The main problem with previous work on High-Level Synthesis (HLS) Design Space Exploration (DSE) is that the given behavioral description is assumed to be stable and thus, that it has been fully refined a priori. For many application e.g. Artificial Neural Networks (ANNs) it is not easy to refine the input description as numerous parameters like the number of neurons and layers combined with the duration of the training phase is nontrivial and any changes in these parameters significantly affects the resultant hardware circuit. Thus, this work proposes a tightly integrated two-tier application specific HLS DSE method which explores input parameters of the behavioral description and performs a detailed HLS exploration for the best configurations which meet a set of specified input constraints and then maps the optimal design to a configurable SoC FPGA. A case study using different types of ANNs is presented. The design flow has been fully automated and the experimental results show that our proposed flow is extremely effective.

The interconnect is the Achilles heel of FPGAs. It currently dominates the delay and leads to high power consumption. It is thus, imperative to take it into account when designing complex FPGA systems. In this work, we propose a learning-based method for data-flow systems build out of multiple individual components directly connected and find a set of optimal configurations with unique area vs. throughput trade-offs by time-multiplexing their interconnects. These type of configurations are prevalent in FPGA designs where one block streams data to the next one, i.e., jpeg encoders. One uniqueness of this work is that it uses advanced features of state-of-the-art HLS tools that enable automatic pin multiplexing. This feature implies that logic IO ports are time multiplexed automatically, which affects not only the performance of the design, but also the area, and the interconnect complexity, leading to system configurations with unique area vs. performance trade-offs. Pin multiplexing is not feasible at the RT-level where each design has to be manually optimized. Experimental results show that the method is accurate and fast when compared to an exhaustive search as well as other state-of-the-art methods.

Logic locking is an intellectual property (IP) protection technique that prevents IP piracy, reverse engineering and overbuilding attacks by the untrusted foundry or end-users. Existing logic locking techniques are all based on locking the functionality; the design/chip is nonfunctional unless the secret key has been loaded. Existing techniques are vulnerable to various attacks, such as sensitization, key-pruning, and signal skew analysis enabled removal attacks. In this paper, we propose a tenacious and traceless logic locking technique, TTlock, that locks functionality and provably withstands all known attacks, such as SAT-based, sensitization, removal, etc. TTLock protects a secret input pattern; the output of a logic cone is flipped for that pattern, where this flip is restored only when the correct key is applied. Experimental results confirm our theoretical expectations that the computational complexity of attacks launched on TTLock grows exponentially with increasing key-size, while the area, power, and delay overhead increases only linearly. In this paper, we also coin ``parametric locking," where the design/chip behaves as per its specifications (performance, power, reliability, etc.) only with the secret key in place, and an incorrect key downgrades its parametric characteristics. We discuss objectives and challenges in parametric locking.

With the need to create more energy-efficient hardware, approximate computing has emerged as one solution. Approximate computing exploits the applications' inherent tolerance to inaccuracies to simplify the circuits with lower power/area, while achieving higher performance. One of the main problems with approximate computing is that it is highly data dependent. The resultant approximate architecture heavily depends on the training data. Often random inputs are used. However, the error of the approximate circuit can nevertheless reach intolerable levels in case that the final workload significantly differs from the training data used during the architectural approximation. Thus, in this work, we approximate different designs given as behavioral descriptions(e.g. ANSI-C or SystemC) for High-Level Synthesis (HLS) to be mapped as loosely coupled hardware accelerators onto the reconfigurable fabric of a configurable SoC (CSoC) with different input data distributions (IDD) to obtain a set of approximate micro-architectures optimized for each of the IDD. We then propose a runtime reconfigurable approximate micro-architecture manager (MAM) that constantly monitors the workload distributions of each approximate accelerator and reconfigures the accelerators with the approximate microarchitecture that has been trained with IDD most similar to the current workload in order to keep the error under control. Two versions of the MAM have been developed. The first one runs on software(SW) onto an embedded processor, while the second one is implemented on the approximate accelerator in hardware(HW). Experimental results show that our proposed framework can control the error within the specified threshold value very efficiently compared to keeping the approximate accelerator constant, while reducing the energy by up to 50%.

This work presents a method to characterize heterogeneous hardware/software systems mapped onto Configurable SoCs (CSoC) in situ, where in situ implies that the CSoC being characterized is also the final target platform. The result of our proposed method is a trade-off curve of different configurations with unique area vs. performance characteristics, each of which uses a different micro-architecture for the accelerators. Our work has been prototyped on a DE1-SoC FPGA board containing a Cyclone V SoC FPGA with two ARM cores and reconfigurable fabric onto which the complete trade-off curves with dominating designs for each BIP are mapped. A fast heuristic method is proposed, which compared to an exhaustive search method, leading to the optimal solution, is slightly worse while on average 15.2× faster, showing that it can lead to very good results quickly. The proposed method is also compared to a simulation-based offline method. In situ characterization is able to speed up the exploration by on average 25.6×, while being more accurate.

High-level synthesis has some distinct advantages over traditional RT-level VLSI design. One key advantage is its ability to generate microarchitectures with unique area versus performance tradeoffs for the same behavioral description by setting different synthesis options. This is typically called design space exploration (DSE). One of the main ways to explore the design space for a particular behavioral description is by varying the amount of resource sharing allowed. For application-specified integrated circuits, increasing the amount of resource sharing normally leads to slower, but smaller designs, while decreasing the amount of resource sharing, leads to faster, but larger designs as the behavioral description can be further parallelized. In the field-programmable gate array (FPGA) case, this is normally not the case as sharing functional units (FUs) requires the insertion of multiplexers, which are very costly in terms of look up tables, while typical FUs, e.g., adders can very efficiently be mapped on the FPGAs' resources and multipliers can be directly mapped to DSP macros. Hence, for the FPGA case, it traditionally does not make sense to explore the design space by varying the degree of resource sharing. This paper enables the DSE for FPGAs through resource sharing by fixing the bitwidth of selected internal variables and hence limiting the size of some FUs in the design. As it will be shown, the area savings from using smaller FUs, now outweighs the cost of the multiplexers and hence it is possible to achieve smaller microarchitectures. This comes at the expense of introducing potential overflow errors in the design. Experimental results show that our method enables the DSE of FPGAs using resource sharing and measures the error introduced for different types of input data distributions, showing that in some cases the error can be negligible, while in other cases it can be considerable.

This works presents a Design Space Exploration (DSE) method for Behavioral IPs (BIPs) given in ANSI-C or SystemC to find the smallest micro-architecture for a specific target latency. Previous work on High-Level Synthesis (HLS) DSE mainly focused on finding a tradeoff curve with Pareto-optimal designs. HLS is, however, a single process (component) synthesis method. Very often, the latency of the components requires a specific fixed latency when inserted within a larger system. This work presents a fast multi-threaded method to find the smallest micro-architecture for a given BIP and target latency by discriminating between all different explorationknobsand exploring these concurrently. Experimental results show that our proposed method is very effective and comprehensive results compare the quality of results vs. the speedup of your proposed explorer.

Many classes of applications exhibit significant tolerance to inaccuracies in their computations. Some examples include image processing, multimedia applications, and machine learning. These inaccuracies can be exploited to build circuits with smaller area, lower power, and higher performance. Most previous work restricts the approximate optimizations to a particular level of abstraction or step within the VLSI process. This paper shows that a combined multilevel approach is far more superior. Thus, this paper exploits different optimizations visible only at each particular level, leading to better results than single-level methods. Moreover, approximate computing is highly data-dependent. Therefore, in this paper, we study the stability of the approximate circuits when the circuit is optimized for a particular data distribution and the final workload differs from it. Previous work mainly considers a single input data distribution and that this distribution is equal to the final workload. Results show that our proposed method can find better and more optimal configurations compared with previous work and can achieve circuits, which are more robust in environments with dynamic workloads.

This work shows that behavioral IPs (BIPs) are often over-designed when used in heterogenous Multi-Procesosr SoCs (MPSoCs) mainly because they are designed and optimized separately. When instantiated in an MPSoC, these IPs often haven to wait for data from the master and also wait to gain access to the bus to return the results. Behavioral IPs have the advantage over traditional RTL-based IPs that they can be re-synthesized with different constraints, which allows the generation of micro-architectures with unique area vs. performance trade-offs. This work leverages this and introduces a method to automatically identify the workload of each behavioral IP mapped as a slave on an MPSoC system and re-synthesizes it to maximize its efficiency, i.e. reduce its area and minimize its idle time, without affecting the overall performance. We show the area can be reduced by up to 26.1% compared to the fastest implementation without any performance degradation and on average by 13.21%. Compared to an exhaustive search our method is only on average 5% worse while on average 16× faster.

This paper presents a dedicated High-Level Synthesis (HLS) Design Space Explorer (DSE) for FPGAs. C-based VLSI design has the advantage over conventional RTL design that it allows the generation of micro-architectures with unique area vs. performance trade-offs without having to modify the original behavioral description (in this work area vs. latency). This is typically done by modifying the Functional Unit (FU) constraint file or setting different synthesis directives e.g. unroll loops or synthesize arrays as RAM or registers. The result of the design space exploration is a set of Pareto-optimal designs. In this work, we first investigate the quality of the exploration results when using the results reported after HLS (in particular the area) to guide the explorer in finding Pareto-optimal designs. We found that due to the nature of how HLS tools pre-characterize, the area and delay of basic logic primitives and the FPGAs internal structure the area results are not accurate and hence making it necessary to perform a logic synthesis after each newly generated design. This in turn leads to unacceptable long running time. This work therefore presents a dedicated DSE for FPGAs based on a pruning with adaptive windowing method to extract the design candidates to be further (logic) synthesized after HLS. The adaptive windowing is based on a learning method inspired from Rival Penalized Competitive Learning (RPCL) model in order to classify which designs need to be synthesized to find the true Pareto-optimal designs. Results show that our method leads to similar results compared to an explorer which performs a logic synthesis for each newly generated design, while being much faster.

Multi-Context Runtime Reconfigurable FPGAs have unique characteristics that make them extremely vulnerable to Hardware Trojan (HT). These FPGA families reconfigure themselves every clock cycle updating the functionality of the data path. A State Transition Controller (STC) typically holds the configuration code for each of the contexts. This architecture makes these type of architectures very efficient, but also extremely vulnerable to malicious alterations across any of the steps from design to fabrication of the FPGA. This work specifically targets the detection, but also the avoidance of HT being triggered in runtime reconfigurable FPGAs and in particular Coarse-Grained Runtime Reconfigurable Arrays (CGRRA). Experimental results show that our proposed method is very effective and has very little power overhead with no net area overhead.

One of the biggest advantages of C-based very large scale integration design over traditional register transfer level is its ability to automatically generate architectures with different area versus performance characteristics without the need of modifying the original behavioral description. Different knobs can be explored to obtain the dominating tradeoff curve (Pareto-front). So far previous works have only focused on exploring one set of knobs or combining all of them together without considering the underlying implications of each of these knobs. This paper presents the first method that accelerates the design space exploration (DSE) by first classifying these knobs and exploring them sequentially, thus reducing the design space to be explored considerably. In particular: 1) local synthesis directives in the form of pragmas inserted directly at the source code and 2) functional units (FUs) number and type. Second, we propose a probabilistic method to further accelerate the DSE by computing the probability of each micro-architecture generated after the pragma exploration stage, to lead to new dominating designs and in turn exploring only those with the highest probabilities. One additional contribution is that the explorer for both knobs are implemented using novel heuristics. The pragma based explorer is based on ant colony optimization, while the FU explorer explores the number and type of FUs in order to further maximize the total amount of resource sharing that can be extracted. Experimental results show that our proposed method finds Pareto-fronts of similar quality than an exploration method optimized for quality of their results, while accelerating the DSE by an average of 12.2×.

A dynamic functional verification method that compares untimed simulations versus timed simulations for synthesizable [high-level synthesis (HLS)] behavioral descriptions (ANSI-C) is presented in this paper. This paper proposes a method that automatically inserts a set of probes into the untimed behavioral description. These probes record the status of internal signals of the behavioral description during an initial untimed simulation. These simulation results are subsequently used as golden outputs for the verification of the internal signals during a timed simulation once the behavioral description has been synthesized using HLS. Our proposed method reports any simulation mismatches and accurately pinpoints any discrepancies between the functional Software (SW) simulation and the timed simulation at the original behavioral description (source code). Our method does not only determine where to place the probes, but is also able to insert different type of probes based on the specified HLS synthesis options in order not to interfere with the HLS process, minimizing the total number of probes and the size of the data to be stored in the trace file in order to minimize the running time. Results show that our proposed method is very effective and extremely simple to use as it is fully automated.

This brief presents a method to map multiple concurrently executing independent tasks onto a coarse-grain reconfigurable architecture (CGRA) with adaptive frequency control to increase the overall throughput and minimize the total area. The commercial CGRA targeted in this brief is embedded as an IP into reconfigurable systems-on-a-chip and is runtime reconfigurable. It is able to reconfigure its tiles every clock cycle by loading new contexts while adapting its clock. Each tile on the CGRA is composed of a certain number of processing elements and has its own adaptive clock domain. This clock is fully adaptive so that it can match the critical path in each context and hence maximize the throughput. The method proposed in this brief effectively maps multiple independent tasks (applications) onto the same tile(s) in order to minimize the total tiles usage, requiring a smaller CGRA IP area, while achieving high throughput. Experimental results show that our method is very effective and that it can reduce the number of tiles used on average by 31.8% while degrading the overall performance by only 5.7% on average compared with the fastest solution which maps each kernel onto its own tiles with its own adaptive clock.

This works targets the detection of temperature triggered HW Trojans, in particular for third party behavioral IPs (3PBIPs) given in ANSI-C. One of the biggest advantages of C-Based VLSI design is its ability to automatically generate architectures with different trade-offs by only setting different synthesis options. This work uses this property to detect temperature-triggered HW Trojan. A complete design flow is presented. It comprises two main phases: (1) In the first phase, a design space explorer generates micro-architectures with different area vs. power trade-offs automatically for the given behavioral IP. (2) The second phase, maps three of these micro-architectures with different power profiles onto a reconfigurable computing board to create a 3-way redundant system. This system combined with a majority voter scheme is used to detect if a HW Trojan is present in the behavioral IP. Having different power profiles implies that each micro-architecture has a different thermal behavior and thus will trigger the HW Trojan at different time intervals. The outputs of the three designs are compared for discrepancies at regular intervals, allowing our method to therefore exactly pinpoint the exact trigger temperature of the HW Trojan. A case study is presented showing the effectiveness of our method.

High-Level Synthesis (HLS) is a single process synthesis method that has shown to produce very good results compared to hand coded RTL, especially for DSP-related applications. At the same time FPGAs are reaching capacities that allow entire systems to be implemented on them. Most of these systems are also DSP-related and make intensive use of the FPGAs' embedded hardmacros (e.g. DSP-blocks). This works presents a method to efficiently allocate DSP-macros in multi-process systems created using HLS in order to minimize the overall area. The proposed method calculates the area sensitivity of each process when its multiply-accumulate (MAC) operations are either mapped onto the FPGA's hardmacro or its configurable resources and allocates the available hardmacros across all processes. Experimental results show that our method creates very good results compared to the optimal solution at a negligible running time.

This works presents a fast and efficient method to map multiple computationally intensive kernels onto the same FPGA given the FPGA area and communication bandwidth constraint. FPGAs have grown to a size where multiple applications can now be mapped onto a single device. It is therefore important to develop methods than can efficiently decide which kernels of all of the applications under consideration should be mapped onto the FPGA in order to maximize the total system acceleration. Our method shows very good results compared to a standard genetic algorithm, which is often used for multi-objective optimization problems and against the optimal solution obtained using an exhaustive search method. Experimental results show that our method is very scalable and extremely fast.

This paper presents a method to time share the Processing Elements (PEs) of Runtime Coarse Grain Reconfigurable Architectures (CGRA) among multiple processes being executed concurrently onto the same CGRA. Runtime CGRA architectures time-multiplex the data path, creating a set of contexts for each state. These contexts configure the PEs and the routing resources of the CGRA and are typically loaded every clock cycle. The target architecture in this work is a commercial CGRA IP which is embedded as an IP into complex SoCs. Our proposed method analyzes the PE utilization in each context for multi-process systems running concurrently onto the same CGRA and time shares unused PEs assigned to one process with the other processes running in parallel. Our method reduces the total PE usage and hence the size of the CGRA IP and therefore the cost of the SoC. Results show that our method is extremely efficient and can reduce the PE utilization by up to 20% and on average by 14% and is only 2% worse than the optimal solution, while being much faster.

A method to accelerate the Design Space Exploration (DSE) of behavioral descriptions for high-level synthesis based on a divide and conquer method called Divide and Conquer Exploration Algorithm (DC-ExpA) is presented. DC-ExpA parses an untimed behavioral description given in C or SystemC and clusters interdependent operations which are in turn explored independently by inserting synthesis directives automatically in the source code. The method then continues by combining the exploration results to obtain only Pareto-optimal designs. This method accelerates the design space exploration considerably and is compared against two previous methods: an Adaptive Simulated Annealer Exploration Algorithm (ASA-ExpA) that shows good optimality at high runtimes, and a pattern matching method called Clustering Design Space Exploration Acceleration (CDS-ExpA) that is fast but suboptimal. Our proposed method is orthogonal to previous exploration methods that focus on the exploration of resource constraints, allocation, binding, and/or scheduling. Our proposed method on contrary sets local synthesis directives that decide upon the overall architectural structure of the design (e.g., mapping certain arrays to memories or registers). Results show that DC-ExpA explores the design space on average 61% faster than ASA-ExpA, obtaining comparable results indicated by several quality indicators, for example, distance to reference Pareto-front, hypervolume, and Pareto dominance. Compared to CDS-ExpA it is 69% slower, but obtains much betters results compared to the same quality indicators.

This work presents the design of a complex image processing IP developed completely in C. We present the latest advanced in ESL-synthesis and demonstrate its main advantages over conventional RT-level flows. In particular we focus on the ability of behavioral synthesis to shorten the design cycle, perform functional verification and explore quickly the design space obtaining multiple dominating implementations with unique area vs. speed characteristics from an initial untimed behavioral description. A feature extraction process is presented in detailed showing how automatic design space exploration can lead to Pareto optimal (non-dominant) designs ranging from 524,648 gates to 584,868 gates and latencies of 38 to 69 state counts for the smallest and fastest design respectively taking approximately 6.3 hours.

In this paper, a novel thermal-aware dynamic placement planner for reconfigurable systems is presented, which targets transient temperature reduction. Rather than solving time-consuming differential equations to obtain the hotspots, we propose a fast and accurate heuristic model based on power budgeting to plan the dynamic placements of the design statically, while considering the boundary conditions. Based on our heuristic model, we have developed a fast optimization technique to plan the dynamic placements at design time. Our results indicate that our technique is two orders of magnitude faster while the quality of the placements generated in terms of temperature and interconnection overhead is the same, if not better, compared to the thermal-aware placement techniques which perform thermal simulations inside the search engine.

This paper presents a clustering method called clustering design space exploration (CDS-ExpA) to accelerate the architectural exploration of behavioral descriptions in C and SystemC. The trade-offs between faster exploration versus optimality of results are investigated. Two variations of CDS-ExpA were developed: CDS-ExpA(min) and CDS-ExpA(max). CDS-ExpA(min) builds the smallest possible clusters while CDS-ExpA(max) builds the largest possible ones, reducing further the design space. Results show that CDS-ExpA(min) and CDS-ExpA(max) explore the design space 90% and 92% faster on average than a previously developed annealer-based exploration, method, at the expense of not finding 36% and 47% of the Pareto optimal designs and finding the smallest design that is 7% and 9% on average, larger, and the fastest design 28% and 32% slower, respectively.

This paper proposes a new solution to the problem of eliminating hotspots from gate-level netlists as well as examines the effects of timing constraints on the temperature reduction and the overall temperature flattening on the chip. Our core technique consists of three steps. First, a thermal analysis is carried out for logic netlists. (The netlists are assumed to be either isolated or embedded in a larger system with macro-cells.) We then apply a new technique, called isothermal logic partitioning technique ( LP-temp), to the netlists, which essentially builds isothermal logic clusters for the netlists and splits each of the logic clusters exceeding the maximum allowed temperature through its hottest point. This will enlarge a contact point for the hotspot to cool down. Finally, the entire system is replaced using a custom designed temperature-aware floorplanner so that the temperature across the entire system is reduced and flattened. We have developed a thermal-aware design flow, integrating our thermal-aware logic partitioning technique with a timing and thermal-aware floorplanner. Two cases were analyzed: (tight timing) LP-temp combined with the timing and thermal-aware floorplanner, where the partitioned units by LP-temp are replaced locally considering a tight timing budget (5% timing degradation); (loose timing) LP-temp combined with thermal-aware replacement, considering a loose timing budget (10% timing degradation). From experimentations using a set of benchmark designs, it is confirmed that our temperature reduction technique is effective, generating designs with an average of 5.54% and 9.9% more reduction of peak temperature (on average) for the cases of tight and loose timing than that of the designs by a conventional thermal-aware floorplanner without using LP-temp, respectively. We also analyzed the effect of our proposed technique on field-programmable gate arrays (FPGAs) in order to contrast its effectiveness on systems with hotspots on hardmacros. Results show that our technique can reduce the temperature in these systems on average 3.40% and 6.61% for the case of loose and tight timing constraints respectively compared to the thermal-aware floorplanner without using LP-temp .

Very long instruction word processors (VLIW) allow to execute multiple instructions in parallel. At the same time VLIW compilers optimize the source code for maximum performance by grouping as many instructions in parallel as possible. This work addresses the problem of thermal- awareness in VLIW compilers with a temperature control and reduction techniques with an objective of minimizing the peak temperature in the VLIW processor's functional units. We present a main approach and compare it with a technique that inserts NOPs in the assembly code to allow the hottest units to cool down. The main technique, called temperature-aware instruction binding techniqueTemplB, effectively binds the instructions executed in parallel to the coolest possible functional units for a given fixed schedule. It generates, for each instruction in a scheduled instruction word, a priority queue of the coolest functional units that can execute the instruction, and rebinds it to the coolest possible unit, considering the temperature as well as the power consumed by the instruction. From experimentation using a set of benchmark designs, it is confirmed that our temperature reduction technique is effective, lowering down the peak temperature of the initial design by up to 13.82% byTemplB.

The Discrete Element Method (DEM) is a numerical model to describe the mechanical behaviour of discontinuous bodies. It has been traditionally used to simulate particle flows (e.g. sand, sugar), but is becoming more popular as a method to represent solid materials. The DEM is very computationally expensive, but has properties that make it amenable to acceleration by reconfigurable computing. This paper describes the implementation of a dedicated hardware architecture for the DEM implemented on an FPGA, which is capable of giving a speed-zip of about 30 times compared to an optimised software version running on a fast microprocessor.