There was a time - in the dim historical past - when foundries actually made ASICs with only 5000 to 50,000 logic gates. But FPGAs and CPLDs conquered those markets and pushed ASIC silicon toward opportunities with more logic, volume, and speed. Today's largest FPGAs approach the few-million-gate size of a typical ASIC design, and continue to sprout embedded cores, such as CPUs, memories, and interfaces. And given the risks of nonworking nanometer silicon, FPGA costs and time-to-market are looking awfully attractive. So, will FPGAs kill ASICs? ASIC technologists certainly think not. ASICs are themselves sprouting patches of programmable FPGA fabric, and pushing new realms of size and especially speed. New tools claim to have tamed the convergence problems of older ASIC flows. Is the future to be found in a market full of FPGAs with ASIC-like cores? ASICs with FPGA cores? Other exotic hybrids? Our panelists will share their disagreements on these prognostications.

FPGAs have been growing at a rapid rate in the past few years. Their ever-increasing gate densities and performance capabilities are making them very popular in the design of digital systems. In this paper we discuss the state-of-the-art in FPGA physical design. Compared to physical design in traditional ASICs, FPGAs pose a different set of requirements and challenges. Consequently the algorithms in FPGA physical design have evolved differently from their ASIC counterparts. Apart from allowing FPGA users to implement their designs on FPGAs, FPGA physical design is also used extensively in developing and evaluating new FPGA architectures. Finally, the future of FPGA physical design is discussed along with how it is interacting with the latest FPGA technologies.

In the development of new FPGA architectures, a designer must balance speed, density and routing flexibility. In this paper, we discuss a new FPGA architecture based on a patented [1], novel, segmented routing fabric that is targeted to high performance and predictability but does not sacrifice routability or area efficiency. Current segmented architectures allow much flexibility in routing, but incur large delay penalties when a signal has high fanout or must traverse medium to long distances to reach its target. Reducing the number of programmable interconnect points (PIPs) that a signal must traverse to reach its target, while eliminating the RC delay buildup due to signal fanout, improves design performance and offers highly predictable signal delays.

The authors discuss techniques to produce Steiner trees for a large population of nets, e.g., 1000 to 5000 nets, in parallel. This problem arises in iterative-improvement layout strategies that perturb not just a single placed object, but a few thousand objects simultaneously. Such strategies are the focus of work on mapping large placement problems onto massively parallel computers. The authors present a new heuristic that computes Steiner trees for an arbitrary number of nets, each with an arbitrary number of terminals, in essentially constant time given sufficient data-parallel machine resources and a constant distribution of net sizes. Experiments on a Connection Machine demonstrate that it is possible to create good Steiner trees for a few thousand nets in a few hundred milliseconds.>

The authors present some statistical properties of the error introduced in a parallel annealing algorithm for placement. A general parallel algorithm model not specific to any target-machine implementation has been proposed. They have characterized the error in such a general parallel paradigm. Further, they have shown how this error varies with temperature for different parallel configurations. Specifically, they have shown the effect of stream length and the number of streams on the error. They have defined the parallelism factor to illustrate the comparative effects of the two configuration parameters. The effect of error on the convergence of the algorithm was observed. Experimental results are presented to demonstrate the effect of various parameters on the error.>