EDBT 2026 Demo / reviewers in the wild / expert
Jyh-Chwen Lee
dblp:92/3731
· DBLP profile ↗
2ranked-venue papers
0as first author
0since 2021 · last 2003
—ORCID · none
Domains — the database's venue-derived domains; a paper can count in several
Systems, architecture and hardware · 2
Expertise — from the expertise taxonomy: the topics of the expert's papers under the CCF categories. A weight counts papers with recency: 1 for a paper about the topic, 0.3 when the topic is its context, halved every five years.
| Computer architecture, parallel and distributed computing, and storage systems
2 papers |
Electronic design automation · 91% Hardware reliability and fault tolerance · 9% |
Topics — the 2 heaviest of 3, each with the papers that count most for it
| Topic | Weight | Papers | Last | Evidence papers |
|---|---|---|---|---|
Electronic design automation
physical design |
0.1 | 2 | 2003 | Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings · DAC 1999 |
Electronic design automation › physical design › power delivery network design
power/ground network optimization |
0.1 | 2 | 2003 | Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmings · IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 2003 Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings · DAC 1999 |
Methods — techniques the papers use, named apart from their topics
sequence of linear programming · 0.1convex optimization relaxation · 0.0conjugate gradient · 0.0
| Year | Publication | Venue | Position |
|---|---|---|---|
| 2003 | Reliability-constrained area optimization of VLSI power/ground networks via sequence of linear programmingsabstractThis paper presents a new method of sizing the widths of the power and ground routes in integrated circuits so that the chip area required by the routes is minimized subject to electromigration and IR voltage drop constraints. The basic idea is to transform the underlying constrained nonlinear programming problem into a sequence of linear programs. Theoretically, we show (that the sequence of linear programs always converges to the optimum solution of the relaxed convex optimization problem. Experimental results demonstrate that the proposed sequence-of-linear-program method Is orders of magnitude faster than the best-known method based on conjugate gradients with constantly better solution qualities. Sheldon X.-D. Tan, Chuanjin Richard Shi, Jyh-Chwen Lee |
IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. | 3 |
| 1999 | Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear ProgrammingsabstractThis paper presents a new method for determining the widths of the power and ground routes in integrated circuits so that the area required by the routes is minimized subject to the reliability constraints. The basic idea is to transform the resulting constrained nonlinear programming problem into a sequence of linear programs. Theoretically, we show that the sequence of linear programs always converges to the optimum solution of the relaxed convex problem. Experimental results demonstrate that the sequence-of-linear-programming method is orders of magnitude faster than the best-known method based on conjugate gradients, with constantly better optimization solutions. Sheldon X.-D. Tan, Chuanjin Richard Shi, Dragos Lungeanu, Jyh-Chwen Lee, Li-Pen Yuan |
DAC | 4 |